US5255233A
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Non-volatile semiconductor memory device equipped with sense amplifier circuit for discriminating small differential voltage level
Assignee: NEC Corp
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Filing: 1992-06-01
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Granted: 1993-10-19
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Expires: 2012-06-01
Abstract
Abstract An electrically programmable read only memory device changes the threshold voltage level of each memory cell depending upon logic level of a data bit for producing a read-out voltage level indicative of the data bit, and a sense amplifier unit changes the read-out voltage level and a reference voltage level into first and second current by means of first and second current mirror circuits so that a third current mirror circuit controls a voltage level converted from the first current on the basis of a voltage level converted from the second current, wherein the sense amplifier unit further comprises a differential amplifier circuit responsive to the voltage levels respectively converted from the first and second currents so as to discriminate small difference in threshold level of each memory cell, thereby allowing a programming to be completed within relatively short time period.
Inventors
- 👤 Kyouichi Izumi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:07
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/062; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
374 words
A non-volatile semiconductor memory device comprising: a) a memory cell array implemented by a plurality of addressable non-volatile memory cells arranged in rows and columns, and each having one of high and low threshold levels depending upon logic level of a data bit stored therein; b) addressing means provided in association with said memory cell array, and selecting one of said plurality of addressable non-volatile memory cells for producing a read-out data signal of either high or low voltage level at an output node thereof, said read-out data signal being indicative of the threshold level of said one of said plurality of addressable non-volatile memory cells; c) a reference unit operative to produce a reference voltage level regulated between said high and low voltage level of said read-out data signal at an output node thereof; and d) a sense amplifier unit comprising d-1) a data input node coupled with said output node of said addressing means, d-2) a reference node coupled with said output node of said reference unit, d-3) a first gate transistor having a drain node coupled with said data input node, d-4) a second gate transistor having a drain node coupled with said reference node, d-5) a first inverting circuit having an input node coupled with said data input node, and an output node coupled with a gate electrode of said first gate transistor, d-6) a second inverting circuit having an input node coupled with said reference node, and an output node coupled with a gate electrode of said second gate transistor, d-7) a first current mirror circuit coupled between a source of current and a source node of said first gate transistor for controlling a first current, d-8) a second current mirror circuit coupled between said source of current and a source node of said second gate transistor for controlling a second current, d-9) a third current mirror circuit having first and second input nodes respectively supplied with said first and second currents, and responsive to a voltage level converted from said second current for controlling a voltage level at said first input node thereof, and d-10) a differential amplifier circuit responsive to a differential voltage level between said first and second input nodes for producing an output data signal.
Claim 2
Dependent Claim
374 words
A non-volatile semiconductor memory device comprising: a) a memory cell array implemented by a plurality of addressable non-volatile memory cells arranged in rows and columns, and each having one of high and low threshold levels depending upon logic level of a data bit stored therein; b) addressing means provided in association with said memory cell array, and selecting one of said plurality of addressable non-volatile memory cells for producing a read-out data signal of either high or low voltage level at an output node thereof, said read-out data signal being indicative of the threshold level of said one of said plurality of addressable non-volatile memory cells; c) a reference unit operative to produce a reference voltage level regulated between said high and low voltage level of said read-out data signal at an output node thereof; and d) a sense amplifier unit comprising d-1) a data input node coupled with said output node of said addressing means, d-2) a reference node coupled with said output node of said reference unit, d-3) a first gate transistor having a drain node coupled with said data input node, d-4) a second gate transistor having a drain node coupled with said reference node, d-5) a first inverting circuit having an input node coupled with said data input node, and an output node coupled with a gate electrode of said first gate transistor, d-6) a second inverting circuit having an input node coupled with said reference node, and an output node coupled with a gate electrode of said second gate transistor, d-7) a first current mirror circuit coupled between a source of current and a source node of said first gate transistor for controlling a first current, d-8) a second current mirror circuit coupled between said source of current and a source node of said second gate transistor for controlling a second current, d-9) a third current mirror circuit having first and second input nodes respectively supplied with said first and second currents, and responsive to a voltage level converted from said second current for controlling a voltage level at said first input node thereof, and d-10) a differential amplifier circuit responsive to a differential voltage level between said first and second input nodes for producing an output data signal.
Claim 3
Dependent Claim
32 words
A non-volatile semiconductor memory device as set forth in claim 1, in which each of said plurality of addressable non-volatile memory cells is implemented by a floating gate type field effect transistor.
Claim 4
Dependent Claim
102 words
A non-volatile semiconductor memory device as set forth in claim 1, in which said addressing means comprises b-1) a row address decoder unit responsive to row address bits for selecting one of said rows of said memory cell array, b-2) a column selector unit implemented by a plurality of gate transistors, and coupled between said memory cell array and said sense amplifier unit, and b-3) a column address decoder unit responsive to column address bits for allowing said column selector unit to couple one of said columns of said memory cell array with said data input node of said sense amplifier unit.
Claim 5
Dependent Claim
170 words
A non-volatile semiconductor memory device as set forth in claim 3, in which said reference unit comprises c-1) a series combination of a dummy gate transistor and a dummy memory cell coupled between said reference node and a first constant voltage source, said dummy gate transistor being equal in current driving capability to each of said a plurality of gate transistors, said dummy memory cell being equal in current driving capability to each of said addressable non-volatile memory cells, and c-2) a constant voltage producing circuit having an output node coupled with a control gate electrode of said dummy memory cell for producing a first predetermined voltage level at a drain node of said dummy memory cell, said first predetermined voltage level being regulated between a second predetermined voltage level at a drain node of one of said plurality of addressable non-volatile memory cells with said high threshold level and a third predetermined voltage level at a drain node of another addressable non-volatile memory cell with said low threshold level.
Claim 6
Dependent Claim
72 words
A non-volatile semiconductor memory device as set forth in claim 1, in which said first current mirror circuit comprises first and second enhancement type field effect transistors coupled in parallel between a first constant voltage source and said first gate transistor and said first input node, said first and second enhancement type field effect transistors having respective gate electrodes coupled with a drain node of said first enhancement type field effect transistor.
Claim 7
Dependent Claim
72 words
A non-volatile semiconductor memory device as set forth in claim 5, in which said second current mirror circuit comprises third and fourth enhancement type field effect transistors coupled in parallel between said first constant voltage source and said second gate transistor and said second input node, said third and fourth enhancement type field effect transistors having respective gate electrodes coupled with a drain node of said third enhancement type field effect transistor.
Claim 8
Dependent Claim
77 words
A non-volatile semiconductor memory device as set forth in claim 6, in which said third current mirror circuit comprises a fifth enhancement type field effect transistor coupled between said first input node and a second constant voltage source, and a sixth enhancement type field effect transistor coupled between said second input node and said second constant voltage source, said fifth and sixth enhancement type field effect transistors having respective gate electrodes coupled with said second input node.
Claim 9
Dependent Claim
84 words
A non-volatile semiconductor memory device as set forth in claim 7, in which said differential amplifier circuit comprises a first series combination of a first load transistor and a first amplifying transistor coupled between said first and second constant voltage sources, and a second series combination of a second load transistor and a second amplifying transistor coupled between said first and second constant voltage sources, said first and second amplifying transistors having respective gate electrodes coupled with said first and second input nodes, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-10-18 | 1997-04-19 | 1997-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-10-18 | 2001-04-19 | 2001-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-10-18 | 2005-04-19 | 2005-10-19 | $7700.00 | Window Closed / Lapsed |