Semiconductor memory device with redundancy circuits

Claim 2

A semiconductor memory device comprising: a memory cell array having plural memory cells arranged in rows and columns, wherein each of said columns has a column address assigned to it such that N columns (N being an integer not less than 2) out of N×M columns (M being an integer not less than 2) share a common column address out of M column addresses; N I/O data lines which are simultaneously connectable to respective N columns of a common column address; N×M first transfer gates, each having a terminal connected to a respective one of said N×M columns, and each being closed so as to allow a flow of current therethrough when an associated column is selected in response to column selection signals generated from column address input signals; M spare columns, each having a different column address out of said M column addresses assigned thereto; M second transfer gates, each having a terminal connected to each one of said M spare columns, and each being closed so as to allow a flow of current therethrough when an associated spare column is selected in response to column selection signals generated from said column address input signals; N first conductive lines connected to other terminals of said N×M first transfer gates such that M of said N×M first transfer gates coupled to a common I/O data line with respective M column addresses have their other terminals connected to a respective one of said N first conductive lines; N fusible links respectively connected between said N I/O data lines and said N first conductive lines; a second conductive line connected to other terminals of said M second transfer gates; and N electrical connecting means, each for electrically connecting each one of said N I/O data lines to said second conductive line as programmed.

Claim 3

A semiconductor memory device according to claim 1, wherein said N electrical connecting means comprise fusible links.

Claim 4

A semiconductor memory device according to claim 1, wherein each of said N electrical connecting means comprises: a transfer gate transistor; a means for applying a certain voltage to the gate electrode of said transfer gate transistor; and a fusible link connected between said gate electrode of said transfer gate transistor and a reference potential point.

Claim 5

A semiconductor memory device according to claim 1, wherein each of said N electrical connecting means comprises: a transfer gate transistor; a means for applying a certain voltage to the gate electrode of said transfer gate transistor through an inverter; a fusible link connected between an input of said inverter and a supply potential point; and a high resistance element connected between said input of said inverter and a reference potential point.

Claim 6

A semiconductor memory device comprising: a memory cell array having plural memory cells arranged in rows and columns, wherein each of said columns has a column address assigned to it such that N columns (N being an integer not less than 2) out of N×M columns (M being an integer not less than 2) share a common column address out of M column addresses; N I/O data lines which are simultaneously connectable to respective N columns of a common column address; N×M first transfer gates connected respectively between said N×M columns and associated I/O data lines, each being closed so as to allow a flow of current therethrough when an associated column is selected in response to column selection signals generated from column address input signals; M spare columns, each having a different column address out of said M column addresses assigned thereto; M second transfer gates, each having a terminal connected to each one of said M spare columns, and each being closed so as to allow a flow of current therethrough when an associated spare column is selected in response to column selection signals generated from said column address input signals; a conductive line which is connected to other terminals of said M second transfer gates; N electrical connecting means, each for electrically connecting each one of said N I/O data lines to said conductive line as programmed; and N control means, each for controlling M column selection signals associated with M columns, out of said N×M columns, coupled to a common I/O data line, wherein each of said N control means comprises: a column decoder circuit including input terminals for receiving said column address input signals, M output terminals coupled to said M column selection signals, and a power supply terminal; a fusible link connected between a supply potential point and said power supply terminal; M pull-down transistors having their drain terminals connected respectively to said M output terminals, having their source terminals connected to a reference potential point, and having their gate terminals connected to a disabled signal line; and a means responsive to blowing said fusible link for activating said disable signal line.

Claim 7

A semiconductor memory device comprising: a memory cell array having plural memory cells arranged in rows and columns, wherein each of said columns has a column address assigned to it such that N columns (N being an integer not less than 2) out of N×M columns (M being an integer not less than 2) share a common column address out of M column addresses; N I/O data lines which are simultaneously connectable to respective N columns of a common column address; N×M first transfer gates connected respectively between said N×M columns and associated I/O data lines, each being closed so as to allow a flow of current therethrough when an associated column is selected in response to column selection signals generated from column address input signals; M spare columns, each having a different column address out of said M column addresses assigned thereto; M second transfer gates, each having a terminal connected to each one of said M spare columns, and each being closed so as to allow a flow of current therethrough when an associated spare column is selected in response to column selection signals generated from said column address input signals; a conductive line which is connected to other terminals of said M second transfer gates; N electrical connecting means, each for electrically connecting each one of said N I/O data lines to said conductive line as programmed; and N control means, each for controlling M column selection signals associated with M columns, out of said N×M columns, coupled to a common I/O data line, wherein each of said N control means comprises: a column decoder circuit including input terminals for receiving said column address input signals, M output terminals coupled to said M column selection signals, and a power supply terminal; a fusible link connected between a supply potential point and said power supply terminal; M pull-down transistors having their drain terminals connected respectively to said M output terminals, having their source terminals connected to a reference potential point, and having their gate terminals connected to a disabled signal line; and a means responsive to blowing said fusible link for activating said disable signal line.

Claim 8

A semiconductor memory device comprising: a memory cell array having plural memory cells arranged in rows and columns, wherein each of said columns has a first column address and a second column address assigned to it such that N columns (N being an integer not less than 2) out of N×N columns share a common first column address out of N first column addresses and that each said N columns of a common first column address have N second column addresses respectively assigned to them; N I/O data lines which are simultaneously connectable to respective N columns of a common first column address or respective N columns of a common second column address; N×N first transfer gates connected respectively between said N×N columns and associated I/O data lines with regard to first column addresses, each being closed so as to allow a flow of current therethrough when an associated column is selected in response to first column selection signals generated from first column address input signals; N×N second transfer gates, each having a terminal connected to each one of said N×N columns, and each being closed so as to allow a flow of current when an associated column is selected in response to second column selection signals generated from second column address input signals; N spare columns, each having a different second column address out of said N second column addresses assigned thereto and having a common specific first column address assignable thereto by programming a programmable column decoder; N third transfer gates connected respectively between said N spare columns and said N I/O data lines, being closed so as to allow a flow of current therethrough when said specific first column address is selected in place of N first transfer gates associated with said specific first column address, in response to said first column selection signals generated from first column address input signals; N fourth transfer gates, each having a terminal connected to each one of said N spare columns, and each being closed so as to allow a flow of current therethrough when an associated spare column is selected in response to second column selection signals generated from said second column address input signals; N first conductive lines which are connected to other terminals of said N×N second transfer gates such that N of said N×N second transfer gates coupled to a common I/O data line with respective N second column addresses have their other terminals connected to a respective one of said N first conductive lines; N fusible links respectively connected between said N I/O data lines and said N first conductive lines; a second conductive line which is connected to other terminals of said N fourth transfer gates; and N electrical connecting means, each for electrically connecting each one of said N I/O data lines to said second conductive line as programmed.

Claim 9

A semiconductor memory device comprising: a memory cell array having plural memory cells arranged in rows and columns, wherein each of said columns has a first column address and a second column address assigned to it such that N columns (N being an integer not less than 2) out of N×N columns share a common first column address out of N first column addresses and that each said N columns of a common first column address have N second column addresses respectively assigned to them; N I/O data lines which are simultaneously connectable to respective N columns of a common first column address or respective N columns of a common second column address; N×N first transfer gates connected respectively between said N×N columns and associated I/O data lines with regard to first column addresses, each being closed so as to allow a flow of current therethrough when an associated column is selected in response to first column selection signals generated from first column address input signals; N×N second transfer gates, each having a terminal connected to each one of said N×N columns, and each being closed so as to allow a flow of current when an associated column is selected in response to second column selection signals generated from second column address input signals; N spare columns, each having a different second column address out of said N second column addresses assigned thereto and having a common specific first column address assignable thereto by programming a programmable column decoder; N third transfer gates connected respectively between said N spare columns and said N I/O data lines, being closed so as to allow a flow of current therethrough when said specific first column address is selected in place of N first transfer gates associated with said specific first column address, in response to said first column selection signals generated from first column address input signals; N fourth transfer gates, each having a terminal connected to each one of said N spare columns, and each being closed so as to allow a flow of current therethrough when an associated spare column is selected in response to second column selection signals generated from said second column address input signals; N first conductive lines which are connected to other terminals of said N×N second transfer gates such that N of said N×N second transfer gates coupled to a common I/O data line with respective N second column addresses have their other terminals connected to a respective one of said N first conductive lines; N fusible links respectively connected between said N I/O data lines and said N first conductive lines; a second conductive line which is connected to other terminals of said N fourth transfer gates; and N electrical connecting means, each for electrically connecting each one of said N I/O data lines to said second conductive line as programmed.

Claim 10

A semiconductor memory device according to claim 6, wherein said N electrical connecting means comprise fusible links.

Claim 11

A semiconductor memory device according to claim 6, wherein each of said N electrical connecting means comprises: a transfer gate transistor; a means for applying a certain voltage to a gate electrode of said transfer gate transistor; and a fusible link connected between said gate electrode of said transfer gate transistor and a reference potential point.

Claim 12

A semiconductor memory device according to claim 6, wherein each of said N electrical connecting means comprises: a transfer gate transistor; a means for applying a certain voltage to gate electrode of said transfer gate transistor through an inverter; a fusible link connected between an input of said inverter and a supply potential point; and a high resistance element connected between said input of said inverter and a reference potential point.

Claim 13

A semiconductor memory device comprising: a memory cell array having plural memory cells arranged in rows and columns, wherein each of said columns has a first column address and a second column address assigned to it such that N columns (N being an integer not less than 2) out of N×N columns share a common first column address out of N first column addresses and that each of said N columns of a common first column address have N second column addresses respectively assigned thereto; N I/O data lines which are simultaneously connectable to respective N columns of a common first column address or respective N columns of a common second column address; N×N first transfer gates respectively connected between said N×N columns and associated I/O data lines with regard to first column addresses, each being closed so as to allow a flow of current therethrough when an associated column is selected in response to first column selection signals generated from first column address input signals; N×N second transfer gates respectively connected between said N×N columns and associated I/O data lines with regard to second column addresses, each being closed so as to allow a flow of current therethrough when an associated column is selected in response to second column selection signals generated from second column address input signals; N spare columns, each having a different second column address out of said N second column addresses assigned thereto and having a common specific first column address assignable thereto by programming a programmable column decoder; N third transfer respectively connected between said N spare columns and said N I/O data lines, being closed so as to allow a flow of current therethrough, when said specific first column address is selected in place of N first transfer gates associated with said specific first column address in response to first column selection signals generated from first column address input signals; N fourth transfer gates, each having a terminal connected to each one of said N spare columns, and each being closed so as to allow a flow of current therethrough when an associated spare column is selected in response to second column selection signals generated form said second column address input signals; a conductive line which is connected to other terminals of said N fourth transfer gates; N electrical connecting means, each for electrically connecting each one of said N I/O data lines to said conductive line as programmed; and N controls means, each for controlling N second column selection signals associated with N columns, out of said N×N columns, coupled to a common I/O data line with regard to second column addresses, wherein each of said N control means comprises: a column decoder circuit including input terminals for receiving said second column address input signals, N output terminals coupled to said N second column selection signals, and a power supply terminal; a fusible link connected between a supply potential point and said power supply terminal; N pull-down transistors having their drain terminals connected respectively to said N output terminals, having their source terminals connected to a reference potential point, and having their gate terminals connected to a disable signal line; and a means responsive to blowing said fusible link for activating said disable signal line.

Claim 14

A semiconductor memory device comprising: a memory cell array having plural memory cells arranged in rows and columns, wherein each of said columns has a first column address and a second column address assigned to it such that N columns (N being an integer not less than 2) out of N×N columns share a common first column address out of N first column addresses and that each of said N columns of a common first column address have N second column addresses respectively assigned thereto; N I/O data lines which are simultaneously connectable to respective N columns of a common first column address or respective N columns of a common second column address; N×N first transfer gates respectively connected between said N×N columns and associated I/O data lines with regard to first column addresses, each being closed so as to allow a flow of current therethrough when an associated column is selected in response to first column selection signals generated from first column address input signals; N×N second transfer gates respectively connected between said N×N columns and associated I/O data lines with regard to second column addresses, each being closed so as to allow a flow of current therethrough when an associated column is selected in response to second column selection signals generated from second column address input signals; N spare columns, each having a different second column address out of said N second column addresses assigned thereto and having a common specific first column address assignable thereto by programming a programmable column decoder; N third transfer respectively connected between said N spare columns and said N I/O data lines, being closed so as to allow a flow of current therethrough, when said specific first column address is selected in place of N first transfer gates associated with said specific first column address in response to first column selection signals generated from first column address input signals; N fourth transfer gates, each having a terminal connected to each one of said N spare columns, and each being closed so as to allow a flow of current therethrough when an associated spare column is selected in response to second column selection signals generated form said second column address input signals; a conductive line which is connected to other terminals of said N fourth transfer gates; N electrical connecting means, each for electrically connecting each one of said N I/O data lines to said conductive line as programmed; and N controls means, each for controlling N second column selection signals associated with N columns, out of said N×N columns, coupled to a common I/O data line with regard to second column addresses, wherein each of said N control means comprises: a column decoder circuit including input terminals for receiving said second column address input signals, N output terminals coupled to said N second column selection signals, and a power supply terminal; a fusible link connected between a supply potential point and said power supply terminal; N pull-down transistors having their drain terminals connected respectively to said N output terminals, having their source terminals connected to a reference potential point, and having their gate terminals connected to a disable signal line; and a means responsive to blowing said fusible link for activating said disable signal line.