Semiconductor device with spare memory cells

Claim 2

.A semiconductor memory device comprising a plurality of bit memory sections (BMS-1 to BMS-n) each having a plurality of memory cells arranged on a plurality of columns, a plurality of column select circuits (14-1 to 14-n) coupled with said bit memory sections (BMS-1 to BMS-n), at least one spare memory section (SMS-1, SMS-2; SMS-11 to SMS-ln), characterized in that said spare memory section (SMS-1, SMS-2; SMS-11 to SMS-ln) has spare memories of one column, and characterized by a plurality of first switching means (20-1 to 20-n) coupled with said column select circuit (14-1 to 14-n), at least one second switching means (36; 38) coupled with at least one of said spare memory sections (SMS-1, SMS-2; SMS-11 to SMS-ln), and control means (16-1, 16-2; 74-1 to 74-n) programmable to turn off said first switching means (20-1) and at the samd time turn on said second switching means (36; 37) in response a specific one of column select signals for selecting columns of said bit memory sections (BMS-1 to BMS-n).

Claim 3

A semiconductor memory device according to claim 1, wherein said control means (16-1, 16-2) includes a plurality of logic circuits (38-1 to 38-i) whose output terminals are each connected to a corresponding one of said first switching means (20-1 to 20-i), a plurality of spare signal generating circuits (32-1 to 32-i) programmable to generate one of two signals having different logic levels, said spare signal generating circuits being respectively coupled at the output terminals with the first input terminals of said logic circuits (38-1 to 38-i), and an address designating circuit (34) programmable to have a specific address, said address designating circuit having an output terminal connected to the second input terminals of said logic circuits (38-1 to 38-i).

Claim 4

A semiconductor memory device according to claim 2, wherein said address designating circuit (34) is formed of resistive means (50) and a plurality of parallel circuits serially connected to each other and to said resistive means (50) and each having a pair of series circuits each formed of a switching element (52 to 59) and a fuse element (60 to 67), said specified address being allotted to said address designating circuit (34) by selectively burning out said fuse elements (60 to 67), whereby said control means (16-1, 16-2; 74-1 to 74-n) produces a control signal, when receiving said specified address, to turn off one of said first switching means (20-1 to 20-n) and turn off said second switching means (36; 37).

Claim 5

A semiconductor memory device according to claim 3, wherein when all the fusible elements (60 to 70) are kept alive, said control means (16-1, 16-2) produces a control signal to turn on all of said first switching means (20-1 to 20-i) and turn off said second switching means (36).

Claim 6

A semiconductor memory device according to claim 2, wherein each of said signal generating circuits (32-1 to 32-i) includes an inverter formed of CMOS transistors, a fusible element connected in series with a current path of said CMOS transistors, and a flip-flop circuit having a input terminal connected to an output terminal of said inverter and an output terminal connected to one of said logic circuits (38-1 to 38-i).

Claim 7

A semiconductor memory device according to claim 1, wherein said address designating circuit (34) is formed of resistive means (50) and a plurality of parallel circuits serially connected to each other and to said resistive means (50) and each having a pair of series circuits each formed of a switching element (52 to 59) and a nonvolatile memory element (60 to 67), a specified address being allotted to said address designating circuit (34) by selectively setting said nonvolatile memory elements (60 to 70) into nonconductive states, whereby said control means (16-1, 16-2; 74-1 to 74-n) produces a control signal, when receiving said specified address, to turn off one of said first switching means (20-1 to 20-n) and turn off said second switching means (36; 37).

Claim 8

A semiconductor memory device according to claim 2, wherein when all the nonvolatile memory elements (60 to 70) are kept in the conductive state, said control means (16-1, 16-2) produces a control signal to turn on all of said first switching means (20-1 to 20-i) and turn off said second switching means (36).

Claim 9

A semiconductor memory device comprising a plurality of bit memory sections (BMS-1 to BMS-n) each having a plurality of memory cells arranged on a plurality of columns, a plurality of column select circuits (14-1 to 14-n) coupled respectively with said bit memory sections (BMS-1 to BMS-n), and spare memory sections (SMS-1, SMS-2; SMS-11 to SMS-ln) each having a plurality of spare memory cells, characterized in that said spare memory sections (SMS-l, SMS-2; SMS-11 to SMS-ln) each have spare memory cells of one column, and characterized by further comprising a plurality of first switching means (20-1 to 20-n) each provided for a corresponding one of said bit memory sections (BMS-1 to BMS-n) and coupled with said column select circuits (14-1 to 14-n), a plurality of second switching means (36; 37) coupled with said spare memory sections (SMS-l, SMS-2; SMS-11 to SMS-ln), and control means (16-1, 16-2; 74-1 to 74-n) programmable to turn off said first switching means (20-1) and at the same time turn on said second switching means (36; 37) in response to a specific one of column select signals for selecting columns of said bit memory sections (BMS-l to BMS-n).

Claim 10

A semiconductor memory device comprising a plurality of bit memory sections (BMS-1 to BMS-n) each having a plurality of memory cells arranged on a plurality of columns, a plurality of column select circuits (14-1 to 14-n) coupled respectively with said bit memory sections (BMS-1 to BMS-n), and spare memory sections (SMS-1, SMS-2; SMS-11 to SMS-ln) each having a plurality of spare memory cells, characterized in that said spare memory sections (SMS-l, SMS-2; SMS-11 to SMS-ln) each have spare memory cells of one column, and characterized by further comprising a plurality of first switching means (20-1 to 20-n) each provided for a corresponding one of said bit memory sections (BMS-1 to BMS-n) and coupled with said column select circuits (14-1 to 14-n), a plurality of second switching means (36; 37) coupled with said spare memory sections (SMS-l, SMS-2; SMS-11 to SMS-ln), and control means (16-1, 16-2; 74-1 to 74-n) programmable to turn off said first switching means (20-1) and at the same time turn on said second switching means (36; 37) in response to a specific one of column select signals for selecting columns of said bit memory sections (BMS-l to BMS-n).

Claim 11

A semiconductor memory device according to claim 8, wherein each of said control means (16-1, 16-2) includes a logic circuit (38-1) connected at the output terminal to a corresponding one of said first switching means (20-1 to 20-i), a spare signal generating circuit (32-1) programmable to generate one of two signals having different logic levels, said spare signal generating circuit being coupled at the output terminal with the first input terminal of said logic circuit (38-1), and an address designating circuit (34) programmable to have a specific address, said address designating circuit having an output terminal connected to a second input terminal of said logic circuit (38-1).

Claim 12

A semiconductor memory device according to claim 9, wherein said address designating circuit (34) is formed of resistive means (50) and a plurality of parallel circuits serially connected to each other and to said resistive means (50) and each having a pair of series circuits each formed of a switching element (52 to 59) and a fuse element (60 to 67), said specified address being allotted to said address designating circuit (34) by selectively burning out said fuse elements (60 to 67), whereby said control means (74-1 to 74-n) produces a control signal, when receiving said specified address, to turn off one of said first switching means (20-1 to 20-n) and turn off one of said second switching means (36; 37).

Claim 13

A semiconductor memory device according to claim 10, wherein when all the fusible elements (60 to 70) are kept alive, said plurality of control means (74-1 to 74-i) produce control signals to turn on all of said first switching means (20-1 to 20-i) and turn off all of said second switching means (37).

Claim 14

A semiconductor memory device according to claim 9, wherein said signal generating circuit (32-1) includes an inverter formed of CMOS transistors, a fusible element connected in series with a current path of said CMOS transistors, and a flip-flop circuit having an input terminal connected to an output terminal of said inverter and an output terminal connected to said logic circuit (38-1).

Claim 15

A semiconductor memory device according to claim 9, wherein said address designating circuit (34) is formed of resistive means (50) and a plurality of parallel circuits serially connected to each other and to said resistive means (50) and each having a pair of series circuits each formed of a switching element (52 to 59) and a nonvolatile memory element (60 to 67), a specified address being allotted to said address designating circuit (34) by selectively setting said nonvolatile memory elements (60 to 70) into nonconductive states, whereby said control means (16-l, 16-2; 74-1 to 74-n) produces a control signal, where receiving said specified address, to turn off one of said first switching means (20-1 to 20-n) and turn off one of said second switching means (36; 37).

Claim 16

A semiconductor memory device according to claim 9, wherein when all the nonvolatile memory elements (60 to 70) are kept in the conductive state, said plurality of control means (70-1 to 70-n) produce control signals to turn on all of said first switching means (20-1 to 20-n) and turn off all of said second switching means (37).