Electrically erasable and programmable read only memory using stacked-gate cell

Claim 2

An erasable programmable nonvolatile memory device comprising: a plurality of memory cells, each memory cell including a semiconductor region; source and drain regions formed in said semiconductor region; a channel region formed between said source and drain regions; a floating gate formed above said channel region; a first insulating layer disposed between said channel region and said floating gate; a control gate formed above said floating gate; and a second insulating layer disposed between said floating gate and said control gate; means for applying a positive voltage to said control gate for injecting electrons in said floating gate for injecting holes in said floating gate for erasure of said memory cells, wherein said means is connected to said control gate of said memory cells via a word line which is connected to a word line decoder via a transferring MOS transistor, said transferring MOS transistor being formed in a well region of said semiconductor region; and wherein said well region is biased at a level equal to or reversely to a source region of said transferring MOS transistor.

Claim 3

An erasable, programmable nonvolatile memory device as set forth in claim 1, wherein said transferring MOS transistor is designed for operation in a depletion mode.

Claim 4

An erasable programmable nonvolatile memory device comprising: a plurality of memory cells, each memory cell including a semiconductor region defining therein a source region, a drain region, and a channel region defined between said source and drain regions, a floating gate formed above said channel region and insulated therefrom, and a control gate formed above said floating gate and insulated therefrom, each memory cell being designed for writing in a bit data by injecting electrons in said floating gate; and means for applying an erasure voltage to said control gate for lowering a gate junction breakdown voltage at a junction between said semiconductor region and said drain region, and applying a drain voltage for causing breakdown at said junction so as to inject holes in said floating gate for erasure of bit data from said memory cells; wherein said means transfers said erasure voltage through said word line; and wherein said means is connected to said control gate of said memory cells via said word line which is connected to a word line decoder via a transferring MOS transistor, said MOS transistor being formed in a well region of said semiconductor region; and wherein said well region is biased at a level equal to or reversely to a source region of said transferring MOS transistor.

Claim 5

An erasable programmable nonvolatile memory device comprising: a plurality of memory cells, each memory cell including a semiconductor region defining therein a source region, a drain region, and a channel region defined between said source and drain regions, a floating gate formed above said channel region and insulated therefrom, and a control gate formed above said floating gate and insulated therefrom, each memory cell being designed for writing in a bit data by injecting electrons in said floating gate; and means for applying an erasure voltage to said control gate for lowering a gate junction breakdown voltage at a junction between said semiconductor region and said drain region, and applying a drain voltage for causing breakdown at said junction so as to inject holes in said floating gate for erasure of bit data from said memory cells; wherein said means transfers said erasure voltage through said word line; and wherein said means is connected to said control gate of said memory cells via said word line which is connected to a word line decoder via a transferring MOS transistor, said MOS transistor being formed in a well region of said semiconductor region; and wherein said well region is biased at a level equal to or reversely to a source region of said transferring MOS transistor.

Claim 6

An erasable programmable nonvolatile memory device as set forth in claim 3, wherein said transferring MOS transistor is designed for operation in a depletion mode.

Claim 7

An erasable programmable nonvolatile memory device comprising: a plurality of memory cells, each memory cell including a semiconductor region; source and drain regions formed in said semiconductor region; a channel region formed between said source and drain regions; a floating gate formed above said channel region; a first insulating layer disposed between said channel region and said floating gate; a control gate formed above said floating gate; and a second insulating layer disposed between said floating gate and said control gate; means for applying a positive voltage having a first predetermined amplitude to said control gate and a second predetermined voltage to said drain region for injecting electrons in said floating gate for writing data into said memory cells and applying a negative voltage having a third predetermined amplitude lower than said first predetermined amplitude to said control gate and a voltage having said second predetermined voltage to said drain region for injecting holes in said drain region for injecting holes in said floating gate for erasure of data from said memory cells; wherein said means is connected to said control gate of said memory cells via a word line which is connected to a word line decoder via a transferring MOS transistor, said transferring MOS transistor being formed in a well region of said semiconductor region; wherein said well region is biased at a level equal to or reversely to a source region of said transferring MOS transistor; and wherein said first insulating layer and second insulating layer are integrally formed as a common insulating package.

Claim 8

An erasable programmable nonvolatile memory device comprising: a plurality of memory cells, each memory cell including a semiconductor region; source and drain regions formed in said semiconductor region; a channel region formed between said source and drain regions; a floating gate formed above said channel region; a first insulating layer disposed between said channel region and said floating gate; a control gate formed above said floating gate; and a second insulating layer disposed between said floating gate and said control gate; means for applying a positive voltage having a first predetermined amplitude to said control gate and a second predetermined voltage to said drain region for injecting electrons in said floating gate for writing data into said memory cells and applying a negative voltage having a third predetermined amplitude lower than said first predetermined amplitude to said control gate and a voltage having said second predetermined voltage to said drain region for injecting holes in said drain region for injecting holes in said floating gate for erasure of data from said memory cells; wherein said means is connected to said control gate of said memory cells via a word line which is connected to a word line decoder via a transferring MOS transistor, said transferring MOS transistor being formed in a well region of said semiconductor region; wherein said well region is biased at a level equal to or reversely to a source region of said transferring MOS transistor; and wherein said first insulating layer and second insulating layer are integrally formed as a common insulating package.