Patent US5250847A successfully refreshed from Google Patents.
US5250847A
Expired / Lapsed
US
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Stress isolating signal path for integrated circuits
Assignee: NXP USA Inc
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Filing: 1992-08-12
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Granted: 1993-10-05
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Expires: 2012-08-12
Abstract
Abstract A stress isolating signal path having one end of fixed to a bonding pad of an integrated circuit chip and another end which forms a flexible bonding surface is provided. The flexible bonding surface may be bonded to external package components or external circuitry using conventional wire bond, epoxy bond, tape automated bonding, flip chip bonding, or the like. The signal path is formed using conventional semiconductor thin film deposition, patterning, and etching techniques. The signal path comprises a conductive material compatible with batch semiconductor manufacturing technology.
Inventors
- 👤 Ira E. Baskett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:11
CPC Classifications
G; G01; G01P; G01P15/00; G01P15/02; G01P15/08; G01P15/0802; H; H10; H10W; H10W72/00; H10W72/50; H10W72/551; H10W72/552; H10W72/5524
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
79 words
A stress isolated integrated circuit comprising: an integrated circuit having circuitry formed on an upper surface, wherein the circuitry includes an area for receiving an electrical signal; a polysilicon spring formed on the circuitry and having a first end coupled to the arms for receiving an electrical signal and a second end, wherein the first end is affixed to the integrated circuit and the second end is separated from the upper surface of the integrated circuit by a gap.
Claim 2
Dependent Claim
79 words
A stress isolated integrated circuit comprising: an integrated circuit having circuitry formed on an upper surface, wherein the circuitry includes an area for receiving an electrical signal; a polysilicon spring formed on the circuitry and having a first end coupled to the arms for receiving an electrical signal and a second end, wherein the first end is affixed to the integrated circuit and the second end is separated from the upper surface of the integrated circuit by a gap.
Claim 3
Dependent Claim
15 words
The IC of claim 1 wherein the spring allows less vertical motion than horizontal motion.
Claim 4
Dependent Claim
11 words
The IC of claim 1 wherein the spring comprises doped polysilicon.
Claim 5
Independent Claim
140 words
A method of making a stress signal path for a semiconductor integrated circuit comprising: providing a semiconductor wafer having an upper surface; forming a plurality of integrated circuits in the upper surface, wherein each of the integrated circuits includes an area for receiving an electrical signal; covering the upper surface with a sacrificial layer; patterning the sacrificial layer to expose the area for receiving an electrical signal; covering the sacrifial layer and exposed area with a layer of spring material; patterning the layer of spring material to form a signal path having a first portion affixed to the area for receiving an electrical signal and a second portion extends over the sacrificial layer; and removing the sacrificial layer so that the second portion of the signal path is separated from the upper surface of the semiconductor wafer by a gap.
Claim 6
Independent Claim
140 words
A method of making a stress signal path for a semiconductor integrated circuit comprising: providing a semiconductor wafer having an upper surface; forming a plurality of integrated circuits in the upper surface, wherein each of the integrated circuits includes an area for receiving an electrical signal; covering the upper surface with a sacrificial layer; patterning the sacrificial layer to expose the area for receiving an electrical signal; covering the sacrifial layer and exposed area with a layer of spring material; patterning the layer of spring material to form a signal path having a first portion affixed to the area for receiving an electrical signal and a second portion extends over the sacrificial layer; and removing the sacrificial layer so that the second portion of the signal path is separated from the upper surface of the semiconductor wafer by a gap.
Claim 7
Dependent Claim
29 words
The method of claim 4 wherein the step of covering the sacrifial layer and exposed area with a layer of spring material further comprises depositing a layer of polysilicon.
Claim 8
Dependent Claim
30 words
The method of claim 4 wherein the step of covering the sacrifial layer and exposed area with a layer of spring material further comprises depositing a layer of a metal.
Claim 9
Dependent Claim
37 words
The method of claim 4 wherein the step of covering the sacrifial layer and exposed area with a layer of spring material further comprises depositing a layer of a dielectric then film covered by a conductive film.
Claim 10
Dependent Claim
24 words
The method of claim 4 further comprising a forming a bonding material on an upper surface of the second portion of the signal path.
References Cited (Backward Citations)
US3487541A
Cited
US3588628A
Cited
US4881117A
Cited
US4990991A
Cited
US4924292A
Cited
US4994895A
Cited
US4980753A
Cited
US4933743A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-10-04 | 1997-04-05 | 1997-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-10-04 | 2001-04-05 | 2001-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-10-04 | 2005-04-05 | 2005-10-05 | $7700.00 | Window Closed / Lapsed |