Dual rail processors with error checking on I/O reads

Claim 2

A dual processor data processing system with interprocessor error checking, comprising: a first central processing unit executing a series of instructions; a second central processing unit executing said series of instructions in the same order as, independently of, and in synchronism with said first central processing unit; a main memory unit coupled to both of said first and second central processing units; a first data bus coupled to said first central processing unit for receiving data to be input to said first central processing unit; a second data bus coupled to said second central processing unit for receiving data to be input to said second central processing unit; error checking means, coupled to said first and second data busses, for checking data transmitted over said first and second data busses prior to delivery of said data to said first and second central processing units, said error checking means including comparison means for indicating an error when said data on said first and second data busses are unequal, and memory controller means for indicating the presence of an error when said input data on said first and second input busses are unequal; and error isolation means, responsive to an error detected from said error checking means, for analyzing the cause of error while maintaining system synchronization.

Claim 3

A dual processor data processing system with interprocessor error checking, comprising: a first central processing unit executing a series of instructions; a second central processing unit executing said series of instructions in the same order as, independently of, and in synchronism with said first central processing unit; a main memory unit coupled to both of said first and second central processing units; a first data bus coupled to said first central processing unit for receiving data to be input to said first central processing unit; a second data bus coupled to said second central processing unit for receiving data to be input to said second central processing unit; error checking means, coupled to said first and second data busses, for checking data transmitted over said first and second data busses prior to delivery of said data to said first and second central processing units, said error checking means including comparison means for indicating an error when said data on said first and second data busses are unequal, and memory controller means for indicating the presence of an error when said input data on said first and second input busses are unequal, said memory controller means including a primary memory controller coupled to said first data bus and including means for transferring data from said first data bus to said main memory unit, and a mirror memory controller coupled to said second bus and including means for comparing the data from said second data bus with the data from said first data bus for purposes of error checking; and error isolation means, responsive to an error detected from said error checking means, for analyzing the cause of error while maintaining system synchronization.

Claim 4

A dual processor data processing system with interprocessor error checking, comprising: a first central processing unit executing a series of instructions; a second central processing unit executing said series of instructions in the same order as, independently of, and in synchronism with said first central processing unit; a main memory unit coupled to both of said first and second central processing units; a first data bus coupled to said first central processing unit for receiving data to be input to said first central processing unit; a second data bus coupled to said second central processing unit for receiving data to be input to said second central processing unit; error checking means, coupled to said first and second data busses, for checking data transmitted over said first and second data busses prior to delivery of said data to said first and second central processing units, said error checking means including comparison means for indicating an error when said data on said first and second data busses are unequal, and memory controller means for indicating the presence of an error when said input data on said first and second input busses are unequal, said memory controller means including a primary memory controller coupled to said first data bus and including means for transferring data from said first data bus to said main memory unit, and a mirror memory controller coupled to said second bus and including means for comparing the data from said second data bus with the data from said first data bus for purposes of error checking; and error isolation means, responsive to an error detected from said error checking means, for analyzing the cause of error while maintaining system synchronization.

Claim 5

A dual processor data processing system with interprocessor error checking, comprising: a first central processing unit executing a series of instructions; a second central processing unit executing said series of instructions in the same order as, independently of, and in synchronism with said first central processing unit; a main memory unit coupled to both of said first and second central processing units, said main memory unit including means for comparing said addresses transferred from said primary and mirror memory controllers to detect errors in said addresses; a first data bus coupled to said first central processing unit for receiving data to be input to said first central processing unit; a second data bus coupled to said second central processing unit for receiving data to be input to said second central processing unit; error checking means, coupled to said first and second data busses, for checking data transmitted over said first and second data busses prior to delivery of said data to said first and second central processing units, said error checking means including comparison means for indicating an error when said data on said first and second data busses are unequal, and memory controller means for indicating the presence of an error when said input data and said first and second input busses are unequal, said memory controller means including a primary memory controller coupled to said first data bus and including means for transferring data from said first data bus to said main memory unit, and means for transferring memory addresses to said main memory unit, and a mirror memory controller coupled to said second bus and including means for comparing the data from said second data bus with the data from said first data bus for purposes of error checking, and means for transferring memory addresses to said main memory unit; and error isolation means, responsive to an error detected from said error checking means, for analyzing the cause of error while maintaining system synchronization.

Claim 6

A dual processor data processing system with interprocessor error checking, comprising: a first central processing unit executing a series of instructions; a second central processing unit executing said series of instructions in the same order as, independently of, and in synchronism with said first central processing unit; a main memory unit coupled to both of said first and second central processing units, said main memory unit including means for comparing said addresses transferred from said primary and mirror memory controllers to detect errors in said addresses; a first data bus coupled to said first central processing unit for receiving data to be input to said first central processing unit; a second data bus coupled to said second central processing unit for receiving data to be input to said second central processing unit; error checking means, coupled to said first and second data busses, for checking data transmitted over said first and second data busses prior to delivery of said data to said first and second central processing units, said error checking means including comparison means for indicating an error when said data on said first and second data busses are unequal, and memory controller means for indicating the presence of an error when said input data and said first and second input busses are unequal, said memory controller means including a primary memory controller coupled to said first data bus and including means for transferring data from said first data bus to said main memory unit, and means for transferring memory addresses to said main memory unit, and a mirror memory controller coupled to said second bus and including means for comparing the data from said second data bus with the data from said first data bus for purposes of error checking, and means for transferring memory addresses to said main memory unit; and error isolation means, responsive to an error detected from said error checking means, for analyzing the cause of error while maintaining system synchronization.

Claim 7

A dual processor data processing system with interprocessor error checking, comprising: a first central processing unit executing a series of instructions; a second central processing unit executing said series of instructions in the same order as, independently of, and in synchronism with said first central processing unit; a main memory unit coupled to both of said first and second central processing units; a first data bus coupled to said first central processing unit for receiving data to be input to said first central processing unit; a second data bus coupled to said second central processing unit for receiving data to be input to said second central processing unit; error checking means, coupled to said first and second data busses, for checking data transmitted over said first and second data busses prior to delivery of said data to said first and second central processing units, said error checking means including comparison means for indicating an error when said data on said first and second data busses are unequal, and memory controller means for indicating the presence of an error when said input data on said first and second input busses are unequal, said memory controller means including a primary memory controller coupled to said first data bus and including means for transferring data from said first data bus to said main memory unit, said primary memory controller including means for transferring data from said main memory unit to said first data bus, and a mirror memory controller coupled to said second bus and including means for comparing the data from said second data bus with the data from said first data bus for purposes of error checking, said mirror memory controller including means for transferring data from said main memory unit to said second data bus; and error isolation means, responsive to an error detected from said error checking means, for analyzing the cause of error while maintaining system synchronization.

Claim 8

A dual processor data processing system with interprocessor error checking, comprising: a first central processing unit executing a series of instructions; a second central processing unit executing said series of instructions in the same order as, independently of, and in synchronism with said first central processing unit; a main memory unit coupled to both of said first and second central processing units; a first data bus coupled to said first central processing unit for receiving data to be input to said first central processing unit; a second data bus coupled to said second central processing unit for receiving data to be input to said second central processing unit; error checking means, coupled to said first and second data busses, for checking data transmitted over said first and second data busses prior to delivery of said data to said first and second central processing units, said error checking means including comparison means for indicating an error when said data on said first and second data busses are unequal, and memory controller means for indicating the presence of an error when said input data on said first and second input busses are unequal, said memory controller means including a primary memory controller coupled to said first data bus and including means for transferring data from said first data bus to said main memory unit, said primary memory controller including means for transferring data from said main memory unit to said first data bus, and a mirror memory controller coupled to said second bus and including means for comparing the data from said second data bus with the data from said first data bus for purposes of error checking, said mirror memory controller including means for transferring data from said main memory unit to said second data bus; and error isolation means, responsive to an error detected from said error checking means, for analyzing the cause of error while maintaining system synchronization.