Circuit configuration for signal testing of functional units of integrated circuits

Claim 1

A circuit configuration for testing functional units in digital integrated circuits by means of test signals, comprising: a plurality of selection devices; each of said selection devices including first, second, third and fourth transistors each having an emitter, a collector and a base; said emitters of said first, second and third transistors of each of said selection devices being coupled to one another; a resistor connected to said emitter of said fourth transistor, said coupled emitters of said first, second and third transistors being connected through an emitter-to-collector path of said fourth transistor and said resistor to a first supply voltage potential; said collectors of said first and second transistor being connected to a second supply voltage potential; said base of said first transistor being a connection for a selection signal, and said base of said second transistor being a connection for a signal to be tested; said base of said third transistor being connected to a third supply voltage potential; said base of said fourth transistor being connected to a fourth supply voltage potential; and a further resistor, each of said collectors of said third transistors of said selection devices being connected to the second supply voltage potential through said further resistor.