Patent US5248628A successfully refreshed from Google Patents.
US5248628A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating a semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1992-06-09
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Granted: 1993-09-28
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Expires: 2012-06-09
Abstract
Abstract A semiconductor memory device wherein at least one of a storage node contact hole and a bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over a gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive material embedded up to a level higher than the gate electrode in the first contact hole which is contacted with the electrically conductive material, the conductive material being exposed by etching a part of the second inter-layer insulating film, whereby the size of the memory device can be made small and the reliability can be improved. Further, a capacitor is formed in a layer higher than a bit line thereby to facilitate the processing of a storage node electrode to increase the capacitor area and to improve the reliability since it is unnecessary to carry out patterning a plate electrode within a cell array. With the above construction, a short-circuiting between the embedded layers is removed and a good quality of the second inter-layer insulating film is formed.
Inventors
- 👤 Naoko Okabe
- 👤 Satoshi Inoue
- 👤 Kazumasa Sunouchi
- 👤 Takashi Yamada
- 👤 Akihiro Nitayama
- 👤 Hiroshi Takato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 08:07
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
303 words
A method of fabricating a semiconductor memory device comprising the steps of: forming a MOSFET having a gate electrode, source and drain regions of a second electrical conductivity type impurity material formed in a surface of a semiconductor substrate of a first electrical conductivity type material; forming a first inter-layer insulating film over said gate electrode; forming a first contact hole such as to expose a surface of said substrate and to be contacted with at least one of the source and drain regions of said MOSFET; forming a second contact hole such as to expose a surface of said substrate and to be contacted with another of the source and drain regions of said MOSFET; embedding a first electrically conductive layer in said first contact hole up to a position higher than the gate electrode; embedding a second electrically conductive layer in said second contact hole up to a position higher than the gate electrode; forming a second inter-layer insulating film over said first and second electrically conductive layers; forming a third contact hole as a storage node contact hole by selectively removing part of said second inter-layer insulating film to expose the first electrically conductive layer; forming a storage node electrode connected to one of the source and drain regions of the MOSFET through said storage node contact hole; forming a capacitor insulating film over said storage node electrode; forming a plate electrode over said capacitor insulating film; forming a third inter-layer insulating film over said plate electrode; forming a fourth contact hole as a bit line contact hole by selectively removing part of said second and third inter-layer insulating films to expose the second electrically conductive layer; and forming a bit line connected to another of the source and drain regions of said MOSFET through said bit line contact hole.
Claim 2
Independent Claim
303 words
A method of fabricating a semiconductor memory device comprising the steps of: forming a MOSFET having a gate electrode, source and drain regions of a second electrical conductivity type impurity material formed in a surface of a semiconductor substrate of a first electrical conductivity type material; forming a first inter-layer insulating film over said gate electrode; forming a first contact hole such as to expose a surface of said substrate and to be contacted with at least one of the source and drain regions of said MOSFET; forming a second contact hole such as to expose a surface of said substrate and to be contacted with another of the source and drain regions of said MOSFET; embedding a first electrically conductive layer in said first contact hole up to a position higher than the gate electrode; embedding a second electrically conductive layer in said second contact hole up to a position higher than the gate electrode; forming a second inter-layer insulating film over said first and second electrically conductive layers; forming a third contact hole as a storage node contact hole by selectively removing part of said second inter-layer insulating film to expose the first electrically conductive layer; forming a storage node electrode connected to one of the source and drain regions of the MOSFET through said storage node contact hole; forming a capacitor insulating film over said storage node electrode; forming a plate electrode over said capacitor insulating film; forming a third inter-layer insulating film over said plate electrode; forming a fourth contact hole as a bit line contact hole by selectively removing part of said second and third inter-layer insulating films to expose the second electrically conductive layer; and forming a bit line connected to another of the source and drain regions of said MOSFET through said bit line contact hole.
Claim 3
Dependent Claim
49 words
A method of fabricating a semiconductor memory device as set forth in claim 1, wherein said first contact forming step includes a step of etching said first inter-layer insulating film so that a sectional area of said first contact hole is larger at portions higher than said gate electrode.
Claim 4
Dependent Claim
62 words
A method of fabricating a semiconductor memory device as set forth in claim 1 or 2, further comprising a step of etching said first inter-layer insulating film down to a level lower than a top surface of the first embedded electrically conductive layer after the second electrically conductive layer embedding step and prior to the formation of said second inter-layer insulating film.
Claim 5
Independent Claim
303 words
A method of fabricating a semiconductor memory device comprising the steps of: forming a MOSFET having a gate electrode, source and drain regions of a second electrical conductivity type impurity material formed on a surface of a semiconductor substrate of a first electrical conductivity type material; forming a first inter-layer insulating film over said gate electrode; forming a first contact hole such as to expose a surface of said substrate and to be contacted with at least one of the source and drain regions of said MOSFET; forming a second contact hole such as to expose a surface of said substrate and to be contacted with another of the source and drain regions of said MOSFET; embedding a first electrically conductive layer in said first contact hole up to a position higher than the gate electrode; embedding a second electrically conductive layer in said first contact hole up to a position higher than the gate electrode; forming a second inter-layer insulating film over said first and second electrically conductive layers; forming a third contact hole as a bit line contact hole by selectively removing part of said second inter-layer insulating film to expose the first electrically conductive layer; forming a bit line connected to one of the source and drain regions of the MOSFET through said bit line contact hole; forming a third inter-layer insulating film over said bit line; forming a fourth contact hole as a storage node contact hole by selectively removing part of said second and third inter-layer insulating films to expose the second electrically conductive layer; forming a storage node electrode connected to another of the source and drain regions of said MOSFET through said storage node contact hole; forming a capacitor insulating film over said storage node electrode; and forming a plate electrode over said capacitor insulating film.
Claim 6
Independent Claim
303 words
A method of fabricating a semiconductor memory device comprising the steps of: forming a MOSFET having a gate electrode, source and drain regions of a second electrical conductivity type impurity material formed on a surface of a semiconductor substrate of a first electrical conductivity type material; forming a first inter-layer insulating film over said gate electrode; forming a first contact hole such as to expose a surface of said substrate and to be contacted with at least one of the source and drain regions of said MOSFET; forming a second contact hole such as to expose a surface of said substrate and to be contacted with another of the source and drain regions of said MOSFET; embedding a first electrically conductive layer in said first contact hole up to a position higher than the gate electrode; embedding a second electrically conductive layer in said first contact hole up to a position higher than the gate electrode; forming a second inter-layer insulating film over said first and second electrically conductive layers; forming a third contact hole as a bit line contact hole by selectively removing part of said second inter-layer insulating film to expose the first electrically conductive layer; forming a bit line connected to one of the source and drain regions of the MOSFET through said bit line contact hole; forming a third inter-layer insulating film over said bit line; forming a fourth contact hole as a storage node contact hole by selectively removing part of said second and third inter-layer insulating films to expose the second electrically conductive layer; forming a storage node electrode connected to another of the source and drain regions of said MOSFET through said storage node contact hole; forming a capacitor insulating film over said storage node electrode; and forming a plate electrode over said capacitor insulating film.
Claim 7
Dependent Claim
49 words
A method of fabricating a semiconductor memory device as set forth in claim 4, wherein said first contact forming step includes a step of etching said first inter-layer insulating film so that a sectional area of said first contact hole is larger at portions higher than said gate electrode.
Claim 8
Dependent Claim
62 words
A method of fabricating a semiconductor memory device as set forth in claim 4 or 5, further comprising a step of etching said first inter-layer insulating film down to a level lower than a top surface of the first embedded electrically conductive layer after the second electrically conductive layer embedding step and prior to the formation of said second inter-layer insulating film.
Claim 9
Dependent Claim
50 words
A method of fabricating a semiconductor memory device as set forth in claim 6, further comprising a thermal oxidization step of oxidizing a surface of the first embedded electrically conductive layer after said first inter-layer insulating film etching step and prior to the formation of said second inter-layer insulating film.
Claim 10
Dependent Claim
41 words
A method of fabricating a semiconductor memory device as set forth in claim 4, wherein said first electrically conductive layer embedding step includes a step of forming said first electrically conductive layer thicker than a depth of said first contact hole.
Claim 11
Dependent Claim
62 words
A method of fabricating a semiconductor memory device as set forth in claim 1 or 2, further comprising a step of etching said first inter-layer insulating film down to a level lower than a top surface of the second embedded electrically conductive layer after the second electrically conductive layer embedding step and prior to the formation of said second inter-layer insulating film.
Claim 12
Dependent Claim
62 words
A method of fabricating a semiconductor memory device as set forth in claim 4 or 5, further comprising a step of etching said first inter-layer insulating film down to a level lower than a top surface of the second embedded electrically conductive layer after the second electrically conductive layer embedding step and prior to the formation of said second inter-layer insulating film.
Claim 13
Dependent Claim
50 words
A method of fabricating a semiconductor memory device as set forth in claim 4, further comprising a thermal oxidization step of oxidizing a surface of the first embedded electrically conductive layer after said first inter-layer insulating film etching step and prior to the formation of said second inter-layer insulating film.
Claim 14
Dependent Claim
41 words
A method of fabricating a semiconductor memory device as set forth in claim 4, wherein said second electrically conductive layer embedding step includes a step of forming said second electrically conductive layer thicker than a depth of said second contact hole.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-09-27 | 1997-03-29 | 1997-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-27 | 2001-03-29 | 2001-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-27 | 2005-03-29 | 2005-09-28 | $7700.00 | Window Closed / Lapsed |