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US5247654A
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Minimum reset time hold circuit for delaying the completion of a second and complementary operation
Assignee: Hewlett Packard Development Co LP
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Filing: 1989-05-19
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Granted: 1993-09-21
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Expires: 2009-05-19
Abstract
Abstract A circuit determines when a given operation has been performed and starts a counter. If a second operation, particularly an operation complementary to the first operation, is initiated before the counter reaches a predetermined value the second operation is held or delayed until the time is elapsed, after which time the second operation completes.
Inventors
- 👤 Mustafa A. Hamid
- 👤 Roy E. Thoma, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 05:02
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/06; G06F3/0601; G06F1/00; G06F1/24; G06F3/0668; G06F3/0671; G06F3/0673
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
127 words
A circuit to delay the completion of a second operation until a time period commenced by the occurrence of a prior first operation has elapsed wherein the first operation and the second operation are complementary, the circuit comprising: means for determining that the first operation has occurred; means coupled and responsive to said first operation occurring means for providing an elapsed time signal which is triggered upon the occurrence of the first operation; means for determining that the second operation is being initiated; and means coupled and responsive to said elapsed time signal and said means for determining that the second operation is being initiated for providing a delay signal to prevent the completion of the second operation until said elapsed time signal reaches a predetermined value.
Claim 2
Dependent Claim
127 words
A circuit to delay the completion of a second operation until a time period commenced by the occurrence of a prior first operation has elapsed wherein the first operation and the second operation are complementary, the circuit comprising: means for determining that the first operation has occurred; means coupled and responsive to said first operation occurring means for providing an elapsed time signal which is triggered upon the occurrence of the first operation; means for determining that the second operation is being initiated; and means coupled and responsive to said elapsed time signal and said means for determining that the second operation is being initiated for providing a delay signal to prevent the completion of the second operation until said elapsed time signal reaches a predetermined value.
Claim 3
Dependent Claim
17 words
The circuit of claim 1, wherein said means for providing an elapsed time signal includes a counter.
Claim 4
Dependent Claim
25 words
The circuit of claim 1, wherein the circuit is a computer circuit and the first operation and the second operation access a given address location.
Claim 5
Dependent Claim
35 words
The circuit of claim 3, wherein said first operation occurred means and said means for determining that the second operation is being initiated include means for determining if the given address location has been accessed.
Claim 6
Dependent Claim
28 words
The circuit of claim 1, wherein the first operation includes the writing of a particular value and the second operation includes the writing of a logically complementary value.
Claim 7
Dependent Claim
28 words
The circuit of claim 5, wherein the writing of said particular value initiates a reset operation and the writing of said logically complementary value terminates the reset operation.
Claim 8
Dependent Claim
171 words
A delay circuit for use in a computer system having a processor, an address bus, a data bus, control signals and an input/output device, the delay circuit comprising: means for determining that a first predetermined data value has been written by said processor to said input/output device; means coupled and responsive to said first data value determining means for providing an elapsed time signal which is triggered upon the writing of said predetermined data value; means for determining that a second predetermined data value is being written by said processor to said input/output device after said first data value has been written, wherein said second predetermined data value is the inverse of said first data value; and means coupled and responsive to said elapsed time signal and said means for determining that a second predetermined data value is being written for providing a delay signal to prevent said processor from completing the writing of said second data value until said elapsed time signal reaches a predetermined value since last being triggered.
Claim 9
Dependent Claim
171 words
A delay circuit for use in a computer system having a processor, an address bus, a data bus, control signals and an input/output device, the delay circuit comprising: means for determining that a first predetermined data value has been written by said processor to said input/output device; means coupled and responsive to said first data value determining means for providing an elapsed time signal which is triggered upon the writing of said predetermined data value; means for determining that a second predetermined data value is being written by said processor to said input/output device after said first data value has been written, wherein said second predetermined data value is the inverse of said first data value; and means coupled and responsive to said elapsed time signal and said means for determining that a second predetermined data value is being written for providing a delay signal to prevent said processor from completing the writing of said second data value until said elapsed time signal reaches a predetermined value since last being triggered.
Claim 10
Dependent Claim
19 words
The delay circuit of claim 7, wherein said first and second data values are written to the same address.
Claim 11
Dependent Claim
35 words
The delay circuit of claim 8, wherein the writing of said first data value initiates a reset operation of the input/output device and wherein the writing of said second data value terminates the reset operation.
Claim 12
Dependent Claim
21 words
The delay circuit of claim 7, wherein said delay signal indicates to the processor that the input/output device is not ready.
Claim 13
Dependent Claim
18 words
The delay circuit of claim 7, wherein the means for providing an elapsed time signal includes a counter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-09-20 | 1997-03-22 | 1997-09-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-20 | 2001-03-22 | 2001-09-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-20 | 2005-03-22 | 2005-09-21 | $7700.00 | Window Closed / Lapsed |