PLDs with high drive capability

Claim 2

A programmable logic device comprising: a first integrated circuit package having P 1 package leads; and a first integrated circuit chip packaged in said first integrated circuit package and having formed thereon a programmable logic circuit having inputs and outputs and having first output driver means for coupling each of said programmable logic circuit outputs to a respective one of said P 1 leads, at least one of said output driver means being capable of supplying at least 64 milliamps in the output low state, said programmable logic circuit having the same architecture as a pre-existing programmable logic device, said pre-existing programmable logic device comprising a second integrated circuit package having P 0 package leads, including G 0 ground leads, said pre-existing programmable logic device further comprising a second integrated circuit chip packaged in said second integrated circuit package and having formed thereon a programmable logic circuit having inputs and outputs and having second output driver means for coupling each of said programmable logic circuit outputs to a respective one of said P 0 leads, none of said second output driver means being capable of supplying more than approximately 24 milliamps in the output low state.

Claim 3

A Programmable logic device according to claim 1, wherein P 1 >P 0 .

Claim 4

A Programmable logic device according to claim 2, wherein G 1 of said P 1 package leads on said first integrated circuit package are ground leads, G 1 >G 0 .

Claim 5

A programmable logic device comprising: a first integrated circuit package having P 1 package leads; and a first integrated circuit chip packaged in said first integrated circuit package and having formed thereon a first programmable logic circuit having inputs and outputs and having first output driver means for coupling each of said first programmable logic circuit outputs to a respective one of said P 1 leads, at least one of said first output driver means being capable of supplying at least 64 milliamps in the output low state, at least one of said first output driver means being further capable of supplying at least 15 milliamps in the output high state, said first programmable logic circuit having at least the features of a pre-existing programmable logic circuit formed within a pre-existing programmable logic device, said pre-existing programmable logic device comprising a second integrated circuit package having P 0 package leads, and a second integrated circuit chip packaged in said second integrated circuit package and having the pre-existing programmable logic circuit formed thereon, the pre-existing programmable logic circuit having inputs and outputs and having second output driver means for coupling each of said pre-existing programmable logic circuit outputs to a respective one of said P 0 leads, none of said second output driver means being capable of supplying more than approximately 24 milliamps in the output low state.

Claim 6

A programmable logic device comprising: a first integrated circuit package having P 1 package leads; and a first integrated circuit chip packaged in said first integrated circuit package and having formed thereon a first programmable logic circuit having inputs and outputs and having first output driver means for coupling each of said first programmable logic circuit outputs to a respective one of said P 1 leads, at least one of said first output driver means being capable of supplying at least 64 milliamps in the output low state, at least one of said first output driver means being further capable of supplying at least 15 milliamps in the output high state, said first programmable logic circuit having at least the features of a pre-existing programmable logic circuit formed within a pre-existing programmable logic device, said pre-existing programmable logic device comprising a second integrated circuit package having P 0 package leads, and a second integrated circuit chip packaged in said second integrated circuit package and having the pre-existing programmable logic circuit formed thereon, the pre-existing programmable logic circuit having inputs and outputs and having second output driver means for coupling each of said pre-existing programmable logic circuit outputs to a respective one of said P 0 leads, none of said second output driver means being capable of supplying more than approximately 24 milliamps in the output low state.

Claim 7

A Programmable logic device according to claim 4, wherein at least two of said P 1 package leads are coupled to said first integrated circuit chip to provide ground to said first integrated circuit chip.

Claim 8

A programmable logic device according to claim 5, wherein at least two of said P 1 package leads are coupled to said first integrated circuit chip to provide a power supply voltage to said first integrated circuit chip.

Claim 9

A Programmable logic device according to claim 4, further comprising hysteresis means coupled between one of said P 1 package leads and one of said inputs to said first programmable logic circuit.

Claim 10

A Programmable logic device according to claim 4, further comprising: means for selectably decoupling said one of said first output drivers from said one of said P 1 package leads; and a feedback path for coupling said one of said P 1 package leads to one of said inputs of said first programmable logic circuit.

Claim 11

A programmable logic device according to claim 8, wherein said one of said first output driver means comprises a pull-up device and means for selectably coupling or decoupling said pull-up device to said one of said P 1 package leads when said one of said first output driver means outputs a high logic signal.

Claim 12

A programmable logic device according to claim 4, further comprising ground bounce protection means for protecting said one of said first output driver means from ground bounce.

Claim 13

A programmable logic device comprising: a first integrated circuit package having P 1 package leads; and a first integrated circuit chip packaged in said first integrated circuit package and having formed thereon a first programmable logic circuit having inputs and outputs and having first output driver means for coupling each of said programmable logic circuit outputs to a respective one of said P 1 leads, at least one of said first output driver means being capable of supplying at least 64 milliamps in the output low state, said first integrated circuit chip further having formed thereon a plurality of storage devices each coupled to store a signal from a respective one of said P 1 leads and to provide said stored signal to a respective one of said inputs of said first programmable logic circuit, each of said storage devices including a control input, said control inputs of all of said storage devices being coupled together, said first integrated circuit chip further having formed thereon means for bypassing individually selectable ones of said storage means, said first programmable logic circuit having at least the features of a pre-existing logic circuit formed within a pre-existing programmable logic device, said pre-existing programmable logic device comprising a second integrated circuit package having P 0 package leads, and a second integrated circuit chip packaged in said second integrated circuit package and having the pre-existing programmable logic circuit formed thereon, the pre-existing programmable logic circuit having inputs and outputs and having second output driver means for coupling each of said pre-existing programmable logic circuit outputs to a respective one of said P 0 leads, none of said second output driver means being capable of supplying more than approximately 24 milliamps in the output low state.

Claim 14

A programmable logic device comprising: a first integrated circuit package having P 1 package leads; and a first integrated circuit chip packaged in said first integrated circuit package and having formed thereon a first programmable logic circuit having inputs and outputs and having first output driver means for coupling each of said programmable logic circuit outputs to a respective one of said P 1 leads, at least one of said first output driver means being capable of supplying at least 64 milliamps in the output low state, said first integrated circuit chip further having formed thereon a plurality of storage devices each coupled to store a signal from a respective one of said P 1 leads and to provide said stored signal to a respective one of said inputs of said first programmable logic circuit, each of said storage devices including a control input, said control inputs of all of said storage devices being coupled together, said first integrated circuit chip further having formed thereon means for bypassing individually selectable ones of said storage means, said first programmable logic circuit having at least the features of a pre-existing logic circuit formed within a pre-existing programmable logic device, said pre-existing programmable logic device comprising a second integrated circuit package having P 0 package leads, and a second integrated circuit chip packaged in said second integrated circuit package and having the pre-existing programmable logic circuit formed thereon, the pre-existing programmable logic circuit having inputs and outputs and having second output driver means for coupling each of said pre-existing programmable logic circuit outputs to a respective one of said P 0 leads, none of said second output driver means being capable of supplying more than approximately 24 milliamps in the output low state.

Claim 15

A programmable logic device according to claim 11, wherein each of said storage devices is a transparent latch.

Claim 16

A programmable logic device comprising: a first integrated circuit package having P 1 package leads; a first integrated circuit chip packaged in said first integrated circuit package and having formed thereon a first programmable logic circuit having inputs and outputs and having first output driver means for coupling each of said programmable logic circuit outputs to a respective one of said P 1 leads, at least one of said first output driver means being capable of supplying at least 64 milliamps in the output low state, each given one of said first output driver means comprises a pull-up device and means for selectably coupling or decoupling said pull-up device to said respective one of said P 1 package leads when said given one of said first output driver means outputs a high logic signal; a plurality of transparent input latches each coupled to store a signal from a respective one of said P 1 package leads and to provide said stored signal to a respective one of said inputs of said first programmable logic circuit, each of aid latches including a latch enable input, the latch enable inputs of all of said latches being coupled together; and means for bypassing individually selectable ones of said transparent input latches, said programmable logic circuit having at least the features of a pre-existing programmable logic circuit formed within a pre-existing programmable logic device, said pre-existing programmable logic device comprising a second integrated circuit package having P 0 package leads, and a second integrated circuit chip packaged in said second integrated circuit package and having the pre-existing programmable logic circuit formed thereon, the pre-existing programmable logic circuit having inputs and outputs and having second output driver means for coupling each of said pre-existing programmable logic circuit outputs to a respective one of said P 0 leads, none of said second output driver means being capable of supplying more than approximately 24 milliamps in the output low state.

Claim 17

A programmable logic device comprising: a first integrated circuit package having P 1 package leads; a first integrated circuit chip packaged in said first integrated circuit package and having formed thereon a first programmable logic circuit having inputs and outputs and having first output driver means for coupling each of said programmable logic circuit outputs to a respective one of said P 1 leads, at least one of said first output driver means being capable of supplying at least 64 milliamps in the output low state, each given one of said first output driver means comprises a pull-up device and means for selectably coupling or decoupling said pull-up device to said respective one of said P 1 package leads when said given one of said first output driver means outputs a high logic signal; a plurality of transparent input latches each coupled to store a signal from a respective one of said P 1 package leads and to provide said stored signal to a respective one of said inputs of said first programmable logic circuit, each of aid latches including a latch enable input, the latch enable inputs of all of said latches being coupled together; and means for bypassing individually selectable ones of said transparent input latches, said programmable logic circuit having at least the features of a pre-existing programmable logic circuit formed within a pre-existing programmable logic device, said pre-existing programmable logic device comprising a second integrated circuit package having P 0 package leads, and a second integrated circuit chip packaged in said second integrated circuit package and having the pre-existing programmable logic circuit formed thereon, the pre-existing programmable logic circuit having inputs and outputs and having second output driver means for coupling each of said pre-existing programmable logic circuit outputs to a respective one of said P 0 leads, none of said second output driver means being capable of supplying more than approximately 24 milliamps in the output low state.

Claim 18

A programmable logic device comprising: a first integrated circuit package having P 1 package leads; and a first integrated circuit chip packaged in said first integrated circuit package and having formed thereon a programmable logic circuit having inputs and outputs and having first output driver means for coupling each of said programmable logic circuit outputs to a respective one of said P 1 leads, at least one of said first output driver means being capable of supplying at least 64 milliamps in the output low state, said programmable logic circuit comprising a 16V8.

Claim 19

A programmable logic device comprising: a first integrated circuit package having P 1 package leads; and a first integrated circuit chip packaged in said first integrated circuit package and having formed thereon a programmable logic circuit having inputs and outputs and having first output driver means for coupling each of said programmable logic circuit outputs to a respective one of said P 1 leads, at least one of said first output driver means being capable of supplying at least 64 milliamps in the output low state, said programmable logic circuit comprising a 16V8.

Claim 20

A programmable logic device according to claim 14, wherein P 1 =24.

Claim 21

A programmable logic device according to claim 15, wherein at least three (3) of said P 1 package leads are ground leads.

Claim 22

A programmable logic device according to claim 16, wherein exactly 3 of said P 1 package leads are coupled to said chip to provide a power supply voltage to said chip.

Claim 25

A method according to claim 18, wherein said second programmable device includes at least four output drivers capable of supplying at least 64 milliamps in the output low state.

Claim 26

A method according to claim 19, wherein at least four of said package leads on said second programmable logic device are configurable as package inputs, further comprising the step of providing hysteresis on at least four of said package leads on said second programmable logic device which are configurable as package inputs.

Claim 27

The combination of first and second programmable logic devices, said first programmable logic device comprising a first programmable integrated circuit packaged in a first package type, said first integrated circuit package type having P 1 first package leads, said first programmable integrated circuit having a first power node connected to V 1 of said first package leads, a first ground node connected to G 1 of said first package leads, and a plurality of first signal nodes each connected to a respective one of the remainder of said first package leads, said first integrated circuit further including a plurality of first output drivers for driving some of said first signal nodes, none of the output drivers in said first integrated circuit being capable of driving more than approximately 24 milliamps in the output low state, and said second programmable logic device comprising a second programmable integrated circuit packaged in a second package type, said second integrated circuit package type having P 2 second package leads, said second programmable integrated circuit having a second power node connected to V 2 of said second package leads, a second ground node connected to G 2 of said second package leads, and a plurality of second signal nodes each connected to a respective one of the remainder of said second package leads, said second integrated circuit further including a plurality of second output drivers for driving some of said second signal nodes, wherein said second programmable integrated circuit has at least the same architectural features as said first programmable integrated circuit, wherein at least one of said second output drivers is capable of driving 64 milliamps in the output low state, and wherein P 2 >P 1 and G 2 >G 1 .

Claim 28

The combination of first and second programmable logic devices, said first programmable logic device comprising a first programmable integrated circuit packaged in a first package type, said first integrated circuit package type having P 1 first package leads, said first programmable integrated circuit having a first power node connected to V 1 of said first package leads, a first ground node connected to G 1 of said first package leads, and a plurality of first signal nodes each connected to a respective one of the remainder of said first package leads, said first integrated circuit further including a plurality of first output drivers for driving some of said first signal nodes, none of the output drivers in said first integrated circuit being capable of driving more than approximately 24 milliamps in the output low state, and said second programmable logic device comprising a second programmable integrated circuit packaged in a second package type, said second integrated circuit package type having P 2 second package leads, said second programmable integrated circuit having a second power node connected to V 2 of said second package leads, a second ground node connected to G 2 of said second package leads, and a plurality of second signal nodes each connected to a respective one of the remainder of said second package leads, said second integrated circuit further including a plurality of second output drivers for driving some of said second signal nodes, wherein said second programmable integrated circuit has at least the same architectural features as said first programmable integrated circuit, wherein at least one of said second output drivers is capable of driving 64 milliamps in the output low state, and wherein P 2 >P 1 and G 2 >G 1 .

Claim 29

A combination according to claim 21, wherein V 2 >V 1 .

Claim 30

A programmable logic device for use with a common input latch enable signal, comprising: a logic circuit having logic circuit inputs and logic circuit outputs; a plurality of externally connectable leads; and a first plurality of input circuits, each coupled between one of said leads and a respective one of said logic circuit inputs, and each operable in a first mode as a latch operating responsively to said common input latch enable signal or in a second mode as a signal path unresponsive to said common input latch enable signal; and programmable means for causing each of said input circuits individually to operate in selectable said first or second mode.

Claim 31

A programmable logic device for use with a common input latch enable signal, comprising: a logic circuit having logic circuit inputs and logic circuit outputs; a plurality of externally connectable leads; and a first plurality of input circuits, each coupled between one of said leads and a respective one of said logic circuit inputs, and each operable in a first mode as a latch operating responsively to said common input latch enable signal or in a second mode as a signal path unresponsive to said common input latch enable signal; and programmable means for causing each of said input circuits individually to operate in selectable said first or second mode.

Claim 32

A programmable logic device according to claim 23, further comprising a second plurality of output circuits, each coupled between one of said logic circuit outputs and a respective one of said leads to which one of said input circuits is coupled, each of said output circuits comprising means for selectable driving or not driving said respective one of said leads to a desired respective logic level.

Claim 33

A programmable logic device according to claim 24, wherein at least one of said output circuits is capable of driving said respective one of said leads with at least 64 milliamps in the output low state.