IC card having a monitor timer and a reset signal discrimination circuit

Claim 2

An IC card comprising: a CPU for processing data; a data receiving circuit connected to said CPU for receiving external data from a terminal external to said IC card and inputting the external data to said CPU; a data transmitting circuit connected to said CPU for transmitting response data from said CPU to the terminal external to said IC card; a reset receiving means for receiving an external reset signal from the terminal external to said IC card; a monitor timer connected to and reset by said CPU for generating a timer reset signal after a prescribed time has elapsed without being reset by said CPU, said CPU resetting said monitor timer in response to receipt of external data by said data receiving circuit; and a discrimination circuit, connected to said reset receiving means for receiving an external reset signal, to said monitor timer for receiving a timer reset signal, and to said CPU for resetting said CPU in response to receipt of either of an external reset signal and a timer reset signal, for determining, after resetting of said CPU, which of an external reset signal and a timer reset signal has been received by said discrimination circuit, for generating a discrimination signal indicative of the determination, and for holding the discrimination signal for analysis of resetting of said CPU.

Claim 3

An IC card according to claim 1 comprising: a memory for storing data; and a data bus connecting said CPU to said memory.

Claim 4

An IC card according to claim 2 wherein said discrimination circuit outputs the discrimination signal to said data bus.

Claim 5

An IC card according to claim 3 wherein said discrimination circuit includes a first NOR circuit connected to receive the external reset signal, a second NOR circuit connected to receive the timer reset signal and the output of said first NOR circuit, a third NOR circuit connected to receive both the external reset and timer reset signals, and an inverter circuit connected to receive the output of said second NOR circuit, said first NOR circuit connected to receive the output of said second NOR circuit, the output of said third NOR circuit being connected to said CPU, and the output of said inverter circuit being connected to said data bus.

Claim 6

An IC card according to claim 1 wherein said reset receiving means includes an antenna for receiving the external reset signal as an electromagnetic wave.

Claim 7

An IC card according to claim 1 comprising a multiple conductor connector electrically connected to said IC card and including one conductor for receiving the external reset signal.

Claim 8

An IC card comprising: a CPU for processing data, said CPU being reset upon receipt of a stop signal and generating a read signal in response to receipt of a stop signal; a data receiving circuit connected to said CPU for receiving external data from a terminal external to said IC card and inputting the external data to said CPU; a data transmitting circuit connected to said CPU for transmitting response data from said CPU to the terminal external to said IC card; a reset receiving means for receiving an external reset signal from the terminal external to said IC card; a monitor timer connected to and reset by said CPU for generating a timer reset signal after a prescribed time has elapsed without being reset by said CPU, said CPU resetting said monitor timer in response to receipt of external data by said data receiving circuit; and a discrimination circuit, connected to said reset receiving means for receiving an external reset signal, to said monitor timer for receiving a timer reset signal, and to said CPU, said discrimination circuit generating a stop signal in response to receipt of either of an external reset signal and a timer reset signal and for supplying the stop signal to said CPU, thereby resetting said CPU, for determining, in response to a read signal generated by said CPU in response to receipt of the stop signal, which of an external reset signal and a timer reset signal has been received by said discrimination circuit, for generating a discrimination signal indicative of the determination, and for holding the discrimination signal for analysis of resetting of said CPU.

Claim 9

An IC card comprising: a CPU for processing data, said CPU being reset upon receipt of a stop signal and generating a read signal in response to receipt of a stop signal; a data receiving circuit connected to said CPU for receiving external data from a terminal external to said IC card and inputting the external data to said CPU; a data transmitting circuit connected to said CPU for transmitting response data from said CPU to the terminal external to said IC card; a reset receiving means for receiving an external reset signal from the terminal external to said IC card; a monitor timer connected to and reset by said CPU for generating a timer reset signal after a prescribed time has elapsed without being reset by said CPU, said CPU resetting said monitor timer in response to receipt of external data by said data receiving circuit; and a discrimination circuit, connected to said reset receiving means for receiving an external reset signal, to said monitor timer for receiving a timer reset signal, and to said CPU, said discrimination circuit generating a stop signal in response to receipt of either of an external reset signal and a timer reset signal and for supplying the stop signal to said CPU, thereby resetting said CPU, for determining, in response to a read signal generated by said CPU in response to receipt of the stop signal, which of an external reset signal and a timer reset signal has been received by said discrimination circuit, for generating a discrimination signal indicative of the determination, and for holding the discrimination signal for analysis of resetting of said CPU.

Claim 10

The IC card according to claim 7 wherein said discrimination circuit includes a first NOR circuit connected to receive the external reset signal, a second NOR circuit connected to receive the timer reset signal and the output of said first NOR circuit, a third NOR circuit connected to receive both the external reset and timer reset signals, and an inverter circuit connected to receive the output of said second NOR circuit, said first NOR circuit connected to receive the output of said second NOR circuit, the output of said third NOR circuit being connected to said CPU, and the output of said inverter circuit being connected to said data bus.

Claim 11

The IC card according to claim 8 wherein the output of said inverter circuit is connected to said CPU to receive the read signal, said inverter outputting the discrimination signal in response to receipt of the read signal.