EP0335494A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Watchdog timer
Assignee: Advanced Micro Devices Inc
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Filing: 1989-02-21
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Granted: —
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Expires: 2009-02-21
Abstract
Abstract In a watchdog timer, the selected codes identifying the format of a watchdog timer algorithm, such as the intervals within which a watchdog timer status must be issued by the host processor, are supplied as hardwired preset codes in programmable fuse or read only memory cells that are adapted to be programmed, but are immune from ESD, power glitches and errant software. A programmable code indicating a programmable time interval is also stored in a register protected from errant software when the watchdog timer is enabled. A selector receives the preset code and the programmable code and selects an output code indicating the time interval within which the watchdog timer must be reset by a processor status signal. The selector can be programmed to select only the preset code by supplying a selector control signal through an element that is immune from electrostatic discharge, power glitches and errant software. Also, a code fixing the watchdog timer in an on state can be supplied with ESD-immune cells. The watchdog timer employs a keyed sequence for the watchdog timer status signal.
Inventors
- 👤 Bruce Randal Allen
- 👤 Arthur Benjamin Oliver
- 👤 Robert W. O'dell
- 👤 James E. Bowles
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 08:55
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
108 words
For use with a program controlled processor generating a status signal within preselected time intervals when operating properly, and responsive to a reset signal to reset the processor, an apparatus comprising: means (501,1001), adapted to be programmed, for supplying a hardwired preset code indicating a preset time interval; timing means (203), connected to receive the status signal, for generating a timer code indicating elapsed time since receipt of the status signal; comparing means (Fig. 4), connected to receive the preset code and the timer code, for generating the reset signal when the elapsed time indicated by the timer code exceeds the time interval indicated by the preset code.
Claim 2
Dependent Claim
108 words
For use with a program controlled processor generating a status signal within preselected time intervals when operating properly, and responsive to a reset signal to reset the processor, an apparatus comprising: means (501,1001), adapted to be programmed, for supplying a hardwired preset code indicating a preset time interval; timing means (203), connected to receive the status signal, for generating a timer code indicating elapsed time since receipt of the status signal; comparing means (Fig. 4), connected to receive the preset code and the timer code, for generating the reset signal when the elapsed time indicated by the timer code exceeds the time interval indicated by the preset code.
Claim 3
Dependent Claim
38 words
The apparatus of claim 1, wherein the processor includes a fuse addressing circuit (1009) for programming fuse cells and the means (1001) for supplying a hardwired preset code includes programmable fuse cells writable through the fuse addressing circuit.
Claim 4
Dependent Claim
40 words
The apparatus of claim 1, further including: means (533,613,614), adapted to be programmed, for supplying a hardwired preset enable signal; and means (632), responsive to the hardwired preset enable signal (WDTFIXON), for enabling the apparatus to generate the reset signal.
Claim 5
Dependent Claim
181 words
For use with a program controlled processor generating a status signal within preselected time intervals when operating properly, and responsive to a reset signal to reset the processor, an apparatus comprising: means (501,1001), adapted to be programmed, for supplying a hardwired preset code (WDTFIX(3:0)) indicating a preset time interval; means (500,1005), in communication with the processor, for storing under program control a programmable code (WDSELQ(3:0)) indicating a programmable time interval; selecting means (502,1007), connected to receive the preset code and the programmable code, for selecting the preset code or the programmable code as an output code (WDSEL(3:0)) in response to a selector control signal (FIXSEL); means (521,524,1003) for supplying the selector control signal to the selecting means; timing means (203, Fig. 7), connected to receive the status signal, for generating a timer code (WDTIM(15:0)) indicating elapsed time since receipt of the status signal; comparing means (Fig. 4), connected to receive the output code and the timer code, for generating the reset signal (WDTRST) when the elapsed time indicated by the timer code exceeds the time interval indicated by the output code.
Claim 6
Dependent Claim
181 words
For use with a program controlled processor generating a status signal within preselected time intervals when operating properly, and responsive to a reset signal to reset the processor, an apparatus comprising: means (501,1001), adapted to be programmed, for supplying a hardwired preset code (WDTFIX(3:0)) indicating a preset time interval; means (500,1005), in communication with the processor, for storing under program control a programmable code (WDSELQ(3:0)) indicating a programmable time interval; selecting means (502,1007), connected to receive the preset code and the programmable code, for selecting the preset code or the programmable code as an output code (WDSEL(3:0)) in response to a selector control signal (FIXSEL); means (521,524,1003) for supplying the selector control signal to the selecting means; timing means (203, Fig. 7), connected to receive the status signal, for generating a timer code (WDTIM(15:0)) indicating elapsed time since receipt of the status signal; comparing means (Fig. 4), connected to receive the output code and the timer code, for generating the reset signal (WDTRST) when the elapsed time indicated by the timer code exceeds the time interval indicated by the output code.
Claim 7
Dependent Claim
31 words
The apparatus of claim 4, wherein the means (531) for supplying the selector control signal includes means, adapted to be programmed, for supplying a hardwired signal as the selector control signal.
Claim 8
Independent Claim
24 words
The apparatus of claims 1 or 4 wherein the means for supplying a hardwired preset code comprises depletion implant mask programmable transistors (534,535,536, 537).
Claim 9
Dependent Claim
32 words
The apparatus of claim 6 , wherein the means (531) for supplying the selector control signal includes means, adapted to be programmed, for supplying a hardwired signal as the selector control signal.
Claim 10
Dependent Claim
23 words
The apparatus of claim 6 , wherein the means (531) for supplying the selector control signal comprises a depletion implant mask programmable transistor.
Claim 11
Dependent Claim
38 words
The apparatus of claim 4 , wherein the processor includes a fuse addressing circuit (1009) for programming fuse cells and the means (1001) for supplying a hardwired preset code includes fuse cells writable through the fuse addressing circuit.
Claim 12
Dependent Claim
36 words
The apparatus of claim 9, wherein the means for supplying the selector control signal includes an other fuse cell storing the selector control signal and the other fuse cell is writable through the fuse addressing circuit.
Claim 13
Dependent Claim
36 words
The apparatus of claim 4, further including: means (533,613,614) for supplying a hardwired preset enable signal; and means (632), responsive to the hardwired preset enable signal (WDTFIXON), for enabling the apparatus to generate the reset signal.
Claim 14
Independent Claim
23 words
The apparatus of claims3or 11 wherein the means for supplying the hardwired preset enable signal comprises a depletion implant mask programmable transistor (533).
Claim 15
Independent Claim
42 words
The apparatus of claims 3 or 11 wherein the processor includes a fuse addressing circuit (1009) for programming fuse cells and the means for supplying a hardwired preset enable signal (WDTFIXON) includes a fuse cell (1001) writable through the fuse addressing circuit.
Claim 16
Dependent Claim
70 words
The apparatus of claim 4, further including: means (632), responsive to an enable signal, for enabling the apparatus to generate the reset signal; means (533,613,614) for supplying the enable signal to the means for enabling; and means (302,365,370), connected to the means for storing a programmable code and the receive the enable signal, for preventing the processor from changing the programmable code under program control while the apparatus is enabled.
Claim 17
Independent Claim
15 words
The apparatus of claims 1 or 4,wherein the status signal is a keyed sequence (A5-5A).
Claim 18
Independent Claim
125 words
The apparatus of claims 1 or 4, wherein the timing means (203) includes means (708), responsive to a clear signal (WDTCLR), for clearing the timer code and means (706,713) for incrementing the timer code in order to indicate elapsed time, and wherein the status signal includes a first key and a second key; the apparatus further including means for generating the clear signal comprising: means (300,301), connected to the processor, for detecting generation by the processor of the status signal; means (600,601), responsive to the status signal, for entering a first state if the status signal equals the first key; means (629,603), responsive to the first state and the status signal, for generating the clear signal (WDTCLR) if the status signal equals the second key.
Claim 19
Dependent Claim
35 words
The apparatus of claim 16 , further including means (603,604), responsive to the first state, for generating the reset signal (SOFTRST) if the status signal does not equal the first key or the second key.
Claim 20
Independent Claim
98 words
The apparatus of claims 1 or 4, wherein the processor includes a hardware reset input pin (903) to be connected to an external circuit, and the processor responds differently to a signal supplied to the hardware reset input pin than to the reset signal generated by the apparatus, and further including: means (920,918), connected to receive the reset signal, for generating a reset pulse for supply to the external circuit through the hardware reset input pin; and means (901,902) for discriminating between reset pulse and a signal supplied to the hardware reset input pin from the external circuit.
Claim 21
Dependent Claim
36 words
The apparatus of claim 18, wherein the means for discriminating includes means (908) for generating a hardware reset signal PINPOC in response to a signal supplied to the hardware reset input pin from the external circuit.
Claim 22
Dependent Claim
146 words
For use with a program controlled processor generating a status signal within preselected time intervals when operating properly, and responsive to a reset signal to reset the processor, an apparatus comprising: means (202) for supplying a preselected code indicating the preselected time interval; timing means (203), connected to receive the status signal, for generating a timer code indicating elapsed time since receipt of the status signal; comparing means (Fig. 4), connected to receive the preselected code and the timer code, for generating when enabled the reset signal when the elapsed time indicated by the timer code exceeds the time interval indicated by the preselected code; and means (704) for enabling the timing means (203) in response to an enable signal, including means (533, 1001), adapted to be programmed, for supplying a hardwired enable code and means (632) for connecting the enable code as the enable signal.
Claim 23
Dependent Claim
146 words
For use with a program controlled processor generating a status signal within preselected time intervals when operating properly, and responsive to a reset signal to reset the processor, an apparatus comprising: means (202) for supplying a preselected code indicating the preselected time interval; timing means (203), connected to receive the status signal, for generating a timer code indicating elapsed time since receipt of the status signal; comparing means (Fig. 4), connected to receive the preselected code and the timer code, for generating when enabled the reset signal when the elapsed time indicated by the timer code exceeds the time interval indicated by the preselected code; and means (704) for enabling the timing means (203) in response to an enable signal, including means (533, 1001), adapted to be programmed, for supplying a hardwired enable code and means (632) for connecting the enable code as the enable signal.
Claim 24
Dependent Claim
43 words
The apparatus of claim 20, wherein the processor includes a power-down mode entered in response to a power-down enabling signal PWRDNE*, and further including: means (814), connected to receive and responsive to the enable signal, for preventing assertion of the power-down enabling signal.
Claim 25
Dependent Claim
23 words
The apparatus of claim 20 , wherein the means for supplying a hardwired enable code comprises a depletion implant mask programmable transistor (533).
Claim 26
Dependent Claim
39 words
The apparatus of claim 20 , wherein the processor includes a fuse addressing circuit (1009) for programming fuse cells, and the means for supplying a hardwired enable code includes a fuse cell (1001) writable through the fuse addressing circuit.
Claim 27
Dependent Claim
166 words
For use with a program controlled processor generating a status signal within preselected time intervals when operating properly, and responsive to a reset signal to reset the processor, an apparatus comprising: means (202) for supplying a preselected code indicating the preselected time interval; timing means (300,201,203), connected to receive the status signal, for generating a timer code indicating elapsed time since receipt of the status signal; comparing means (Fig. 4), connected to receive the preselected code and the timer code, for generating when enabled, the reset signal when the elapsed time indicated by the timer code exceeds the time interval indicated by the preselected code; and means (704), responsive to an enable signal, for enabling the apparatus to generate the reset signal; means (632) for supplying the enable signal to the means for enabling; and means (365), connected to the means for supplying a preselected code and the receive the enable signal, for preventing the processor from changing the preselected code while the apparatus is enabled.
Claim 28
Dependent Claim
166 words
For use with a program controlled processor generating a status signal within preselected time intervals when operating properly, and responsive to a reset signal to reset the processor, an apparatus comprising: means (202) for supplying a preselected code indicating the preselected time interval; timing means (300,201,203), connected to receive the status signal, for generating a timer code indicating elapsed time since receipt of the status signal; comparing means (Fig. 4), connected to receive the preselected code and the timer code, for generating when enabled, the reset signal when the elapsed time indicated by the timer code exceeds the time interval indicated by the preselected code; and means (704), responsive to an enable signal, for enabling the apparatus to generate the reset signal; means (632) for supplying the enable signal to the means for enabling; and means (365), connected to the means for supplying a preselected code and the receive the enable signal, for preventing the processor from changing the preselected code while the apparatus is enabled.
Claim 29
Dependent Claim
44 words
The apparatus of claim 24 , wherein the processor includes a power-down mode entered in response to a power-down enabling signal PWRDNE*, and further including: means (814), connected to receive and responsive to the enable signal, for preventing assertion of the power-down enabling signal.
Claim 30
Dependent Claim
208 words
For use with a program controlled processor generating a status signal within preselected time intervals when operating properly, wherein the status signal includes a first key and a second key, and responsive to a reset signal to reset the processor, an apparatus comprising: means (202) for supplying a preselected code indicating the preselected time interval; timing means (300,201,203), connected to receive the status signal, for generating a timer code indicating elapsed time since receipt of the status signal, wherein the timing means includes means (708), responsive to a clear signal (WDTCLR), for clearing the timer code and means (706,713) for incrementing the timer code in order to indicate elapsed time; means (300,301), connected to the processor, for detecting generation by the processor of the status signal; means (600,601), responsive to the status signal, for entering a first state if the status signal equals the first key; means (629,603), responsive to the first state and the status signal, for generating the clear signal if the status signal equals the second key; and comparing means (Fig. 4), connected to receive the preselected code and the timer code, for generating the reset signal when the elapsed time indicated by the timer code exceeds the time interval indicated by the preselected code.
Claim 31
Dependent Claim
208 words
For use with a program controlled processor generating a status signal within preselected time intervals when operating properly, wherein the status signal includes a first key and a second key, and responsive to a reset signal to reset the processor, an apparatus comprising: means (202) for supplying a preselected code indicating the preselected time interval; timing means (300,201,203), connected to receive the status signal, for generating a timer code indicating elapsed time since receipt of the status signal, wherein the timing means includes means (708), responsive to a clear signal (WDTCLR), for clearing the timer code and means (706,713) for incrementing the timer code in order to indicate elapsed time; means (300,301), connected to the processor, for detecting generation by the processor of the status signal; means (600,601), responsive to the status signal, for entering a first state if the status signal equals the first key; means (629,603), responsive to the first state and the status signal, for generating the clear signal if the status signal equals the second key; and comparing means (Fig. 4), connected to receive the preselected code and the timer code, for generating the reset signal when the elapsed time indicated by the timer code exceeds the time interval indicated by the preselected code.
Claim 32
Dependent Claim
34 words
The apparatus of claim 26, further including means (630,604), responsive to the first state, for generating the reset signal (SOFTRST) if the status signal does not equal the first key or the second key.
Claim 33
Dependent Claim
189 words
For use with a program controlled processor generating a status signal within preselected time intervals when operating properly, and responsive to a reset signal to reset the processor, wherein the processor includes a hardware reset input pin (903) connected to an external circuit, and the processor responds differently to a signal supplied to the hardware reset input pin than to the reset signal generated by the apparatus, an apparatus comprising: means (202) for supplying a preselected code indicating the preselected time interval; timing means (300,201,203), connected to receive the status signal, for generating a timer code indicating elapsed time since receipt of the status signal; comparing means (Fig. 4), connected to receive the preselected code and the timer code, for generating the reset signal when the elapsed time indicated by the timer code exceeds the time interval indicated by the preselected code; means (918,920), connected to receive the reset signal, for generating a reset pulse for supply to the external circuit through the hardware reset input pin; and means (901,902) for discriminating between reset pulse and a signal supplied to the hardware reset input pin from the external circuit.
Claim 34
Dependent Claim
189 words
For use with a program controlled processor generating a status signal within preselected time intervals when operating properly, and responsive to a reset signal to reset the processor, wherein the processor includes a hardware reset input pin (903) connected to an external circuit, and the processor responds differently to a signal supplied to the hardware reset input pin than to the reset signal generated by the apparatus, an apparatus comprising: means (202) for supplying a preselected code indicating the preselected time interval; timing means (300,201,203), connected to receive the status signal, for generating a timer code indicating elapsed time since receipt of the status signal; comparing means (Fig. 4), connected to receive the preselected code and the timer code, for generating the reset signal when the elapsed time indicated by the timer code exceeds the time interval indicated by the preselected code; means (918,920), connected to receive the reset signal, for generating a reset pulse for supply to the external circuit through the hardware reset input pin; and means (901,902) for discriminating between reset pulse and a signal supplied to the hardware reset input pin from the external circuit.
Claim 35
Dependent Claim
36 words
The apparatus of claim 36, wherein the means for discriminating includes means (908,901) for generating a hardware reset signal (PINPOC) in response to a signal supplied to the hardware reset input pin from the external circuit.
References Cited (Backward Citations)
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