Patent US5245228A successfully refreshed from Google Patents.
US5245228A
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US
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Level inverter circuit
Assignee: Qimonda AG
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Filing: 1992-03-19
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Granted: 1993-09-14
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Expires: 2012-03-19
Abstract
Abstract A monolithically integrated level inverter circuit converts signals with a first potential difference to signals with a second potential difference. The circuit contains six pairs of transistors.
Inventors
- 👤 Johann Harter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 23:06
CPC Classifications
H; H03; H03K; H03K19/00; H03K17/00; H03K17/10; H03K17/102; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/356113; H03K3/356147
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
522 words
A monolithically integrated level inverter circuit, comprising: first, second, third, fourth, fifth and sixth pairs of transistors each having sources, drains, gates and channel paths; said transistors of said first and second transistor pairs being of a first channel type and said transistors of said third, fourth, fifth and sixth transistor pairs being of a second channel type; the sources of said transistors of said first transistor pair being connected to a first potential; the gates of said transistors of said first transistor pair respectively receiving an input signal and a complementary input signal having levels of the first potential and of a second potential; the drains of said transistors of said first transistor pair each being connected to the source of a respective one of said transistors of said second transistor pair; the gates of said transistors of said second transistor pair being connected to the second potential; the channel path of one of said transistors of said third transistor pair being connected in series with the channel path of one of said transistors of said fourth transistor pair defining a first circuit node for an output signal of the level inverter circuit at the drain of said one transistor of said fourth transistor pair; the channel path of the other of said transistors of said third transistor pair being connected in series with the channel path of the other of said transistors of said fourth transistor pair defining a second circuit node for an output signal of the level inverter circuit at the drain of said other transistor of said fourth transistor pair; the gate of one of said transistors of said fourth transistor pair being connected to the drain of the other of said transistors of said fourth transistor pair, and the gate of the other transistor of said fourth transistor pair being connected to the drain of the one transistor of said fourth transistor pair; the sources of said transistors of said fourth transistor pair being connected to a third potential; the drains of said transistors of said third transistor pair being connected to the second potential; the channel path of one transistor of said fifth transistor pair being connected in series with the channel path of one transistor of said sixth transistor pair, and the channel path of the other transistor of said fifth transistor pair being connected in series with the channel path of the other transistor of said sixth transistor pair; the drains of said transistors of said fifth transistor pair each being connected to the gate of a respective one of said transistors of said third transistor pair; the gates of said transistors of said fifth transistor pair being connected to the second potential; and the gate of one of said transistors of said sixth transistor pair being connected to the source of the other of said transistors of said sixth transistor pair and to one of said circuit nodes, and the gate of the other transistor of said sixth transistor pair being connected to the source of the one transistor of said sixth transistor pair and to the other of said circuit nodes.
Claim 2
Dependent Claim
522 words
A monolithically integrated level inverter circuit, comprising: first, second, third, fourth, fifth and sixth pairs of transistors each having sources, drains, gates and channel paths; said transistors of said first and second transistor pairs being of a first channel type and said transistors of said third, fourth, fifth and sixth transistor pairs being of a second channel type; the sources of said transistors of said first transistor pair being connected to a first potential; the gates of said transistors of said first transistor pair respectively receiving an input signal and a complementary input signal having levels of the first potential and of a second potential; the drains of said transistors of said first transistor pair each being connected to the source of a respective one of said transistors of said second transistor pair; the gates of said transistors of said second transistor pair being connected to the second potential; the channel path of one of said transistors of said third transistor pair being connected in series with the channel path of one of said transistors of said fourth transistor pair defining a first circuit node for an output signal of the level inverter circuit at the drain of said one transistor of said fourth transistor pair; the channel path of the other of said transistors of said third transistor pair being connected in series with the channel path of the other of said transistors of said fourth transistor pair defining a second circuit node for an output signal of the level inverter circuit at the drain of said other transistor of said fourth transistor pair; the gate of one of said transistors of said fourth transistor pair being connected to the drain of the other of said transistors of said fourth transistor pair, and the gate of the other transistor of said fourth transistor pair being connected to the drain of the one transistor of said fourth transistor pair; the sources of said transistors of said fourth transistor pair being connected to a third potential; the drains of said transistors of said third transistor pair being connected to the second potential; the channel path of one transistor of said fifth transistor pair being connected in series with the channel path of one transistor of said sixth transistor pair, and the channel path of the other transistor of said fifth transistor pair being connected in series with the channel path of the other transistor of said sixth transistor pair; the drains of said transistors of said fifth transistor pair each being connected to the gate of a respective one of said transistors of said third transistor pair; the gates of said transistors of said fifth transistor pair being connected to the second potential; and the gate of one of said transistors of said sixth transistor pair being connected to the source of the other of said transistors of said sixth transistor pair and to one of said circuit nodes, and the gate of the other transistor of said sixth transistor pair being connected to the source of the one transistor of said sixth transistor pair and to the other of said circuit nodes.
Claim 3
Dependent Claim
34 words
The level inverter circuit according to claim 1, wherein said transistors of the first channel type are of the n-channel type, and said transistors of the second channel type are of the p-channel type.
Claim 4
Dependent Claim
26 words
The level inverter circuit according to claim 1, wherein the second potential is more positive than the first potential and more negative than the third potential.
Claim 5
Dependent Claim
34 words
The level inverter circuit according to claim 1, wherein said transistors of the first channel type are of the p-channel type, and said transistors of the second channel type are of the n-channel type.
Claim 6
Dependent Claim
26 words
The level inverter circuit according to claim 1, wherein the second potential is more negative than the first potential and more positive than the third potential.
Claim 7
Dependent Claim
27 words
The level inverter circuit according to claim 2, wherein said transistors of the p-channel type have substrate regions connected to the most positive of the three potentials.
Claim 8
Dependent Claim
29 words
The level inverter circuit according to claim 2, wherein said transistors of the p-channel type have substrate regions connected to a potential being more positive than the three potentials.
Claim 9
Dependent Claim
27 words
The level inverter circuit according to claim 4, wherein said transistors of the p-channel type have substrate regions connected to the most positive of the three potentials.
Claim 10
Dependent Claim
29 words
The level inverter circuit according to claim 4, wherein said transistors of the p-channel type have substrate regions connected to a potential being more positive than the three potentials.
Claim 11
Dependent Claim
27 words
The level inverter circuit according to claim 2, wherein said transistors of the n-channel type have substrate regions connected to the most negative of the three potentials.
Claim 12
Dependent Claim
29 words
The level inverter circuit according to claim 2, wherein said transistors of the n-channel type have substrate regions connected to a potential being more negative than the three potentials.
Claim 13
Dependent Claim
27 words
The level inverter circuit according to claim 4, wherein said transistors of the n-channel type have substrate regions connected to the most negative of the three potentials.
Claim 14
Dependent Claim
29 words
The level inverter circuit according to claim 4, wherein said transistors of the n-channel type have substrate regions connected to a potential being more negative than the three potentials.
Claim 15
Dependent Claim
28 words
The level inverter circuit according to claim 1, wherein the input signals are signals having constant potential values being equal to the first potential and the second potential.
Claim 16
Dependent Claim
26 words
The level inverter circuit according to claim 2, wherein the second potential is more positive than the first potential and more negative than the third potential.
Claim 17
Dependent Claim
26 words
The level inverter circuit according to claim 4, wherein the second potential is more negative than the first potential and more positive than the third potential.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1996-09-13 | 1997-03-15 | 1997-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-13 | 2001-03-15 | 2001-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-13 | 2005-03-15 | 2005-09-14 | $7700.00 | Window Closed / Lapsed |