Method and apparatus for buffering electrical signals

Claim 2

A buffer circuit for connection between an input voltage signal and a load, comprising: a first emitter-follower stage through which a load current flows for delivery to the load, said emitter-follower stage comprising a first and a second transistor, each having an emitter, a base, and a collector, said first transistor having its emitter connected to the collector of the second transistor, and being diode-connected with its collector and base interconnected to a supply voltage, and the emitter of said second transistor being connected to a node for connection to the load; a second emitter-follower stage through which a control current flows between the supply voltage and a reference potential, said second emitter-follower stage comprising a third and a fourth transistor, each having an emitter, a base, and a collector, the emitter of the third transistor being connected to the supply voltage, the base of the third transistor being connected to the collector of the second transistor, the emitter of said fourth transistor being connected to the base of said second transistor and to the collector of the third transistor, the base of said fourth transistor being connected to receive said input voltage signal, and the collector of said fourth transistor being connected to the reference voltage; wherein a base-emitter voltage of the first transistor is applied across the base-emitter junction of the third transistor to provide said reference current through said second stage to maintain a voltage across the load that has a fixed relationship to the input voltage signal; and a startup transistor connected in parallel with said third transistor for starting the circuit when no load current is being drawn by driving a current into the load circuit.

Claim 3

The buffer circuit of claim 1 wherein said startup transistor has an emitter, base, and collector, the emitter of said startup transistor being connected to the collector of said third transistor, the collector of said startup transistor being connected to the emitter of said third transistor, and the base of said startup transistor being connected to receive said input voltage signal.

Claim 4

The buffer circuit of claim 1 wherein said startup transistor has an emitter, base, and collector, the emitter and base being connected respectively to the emitter and base of said fourth transistor, and the collector being connected to said supply voltage.

Claim 5

The buffer circuit of claim 1 wherein said buffer circuit has a high input impedance and low output impedance.

Claim 6

The circuit of claim 1 wherein base-emitter voltages of the second and fourth transistors are maintained with fixed values, thereby maintaining a voltage across said load that is substantially equal to the input voltage signal.

Claim 7

The circuit of claim 5 wherein the fixed values of the base-emitter voltages of the second and fourth transistors are substantially equal values.

Claim 8

The circuit of claim 5 wherein the emitter areas of the first and second transistors are substantially equal, and the emitter areas of the third and fourth transistors are substantially equal.

Claim 9

The circuit of claim 1 wherein the emitters of the transistors in the two stages are sized to produce a V BE in the second transistor that is substantially equal to the V BE of the fourth transistor.

Claim 10

The circuit of claim 1 wherein first and second resistors of substantially equal value are connected, respectively between the emitter of said first transistor and the collector of the second transistor, and from the emitter of said second transistor to the load connection node to maintain the V BE of said second transistor substantially equal to the V BE of said fourth transistor.

Claim 11

The circuit of claim 1 wherein first and second resistors of substantially equal value are connected, respectively between the supply voltage and the emitter of said third transistor, and from the collector of said third transistor to the emitter of said fourth transistor to maintain the V BE of the second transistor substantially equal to the V BE of the fourth transistor.

Claim 12

The circuit of claim 1 wherein said first and second transistors are NPN transistors and said third and fourth transistors are PNP transistors.

Claim 13

The circuit of claim 1 further comprisng a pass transistor having an emitter, a base, and a collector, said pass transistor being in series with the second transistor, said pass transistor having its base current mirrored into the base of said second transistor to obtain a first order compensation of the base current of said second transistor.

Claim 14

A circuit for buffering a high output impedance voltage generator circuit that provides an input voltage signal to a low input impedance load circuit, comprising: a first NPN transistor having an emitter, a base, and a collector, the base and collector being connected to a supply voltage; a second NPN transistor having an emitter, a base, and a collector, the collector being connected to the emitter of the first NPN transistor and the emitter being connected to the load circuit; a first PNP transistor having an emitter, a base, and a collector, the emitter being connected to the supply voltage, the base being connected to the emitter of the first NPN transistor, and the collector being connected to the base of the second NPN transistor; a second PNP transistor, having an emitter, a base, and a collector, the emitter being connected to the collector of the first PNP transistor, the collector being connected to a reference potential, and the base being connected to the input voltage signal.

Claim 15

A circuit for buffering a high output impedance voltage generator circuit that provides an input voltage signal to a low input impedance load circuit, comprising: a first NPN transistor having an emitter, a base, and a collector, the base and collector being connected to a supply voltage; a second NPN transistor having an emitter, a base, and a collector, the collector being connected to the emitter of the first NPN transistor and the emitter being connected to the load circuit; a first PNP transistor having an emitter, a base, and a collector, the emitter being connected to the supply voltage, the base being connected to the emitter of the first NPN transistor, and the collector being connected to the base of the second NPN transistor; a second PNP transistor, having an emitter, a base, and a collector, the emitter being connected to the collector of the first PNP transistor, the collector being connected to a reference potential, and the base being connected to the input voltage signal.

Claim 16

The circuit of claim 13 further comprising a startup transistor having an emitter, a base, and a collector, the base being connected to the input voltage signal, the collector being connected to the emitter of the first NPN transistor, and the emitter being connected to the load circuit.

Claim 17

The circuit of claim 14 wherein said startup transistor is a NPN transistor.

Claim 18

The circuit of claim 13 further comprising a startup transistor having an emitter, a base, and a collector, the base being connected to the input voltage signal, the collector being connected to the emitter of the first PNP transistor, and the emitter being connected to the collector of the first PNP transistor.

Claim 19

The circuit of claim 16 wherein said startup transistor is a NPN transistor.

Claim 20

A buffer circuit for connection between an input voltage signal and a load, comprising: a first emitter-follower stage for conducting a load current, said emitter-follower stage comprising a first and a second transistor, each having an emitter, a base, and a collector, said first transistor having its emitter connected to the collector of the second transistor, and being diode-connected with its collector and base interconnected to a supply voltage, and the emitter of said second transistor being connected to a node for connection to the load; a second emitter-follower stage through which a control current flows between the supply voltage and a reference potential, said second emitter-follower stage comprising a third and a fourth transistor, each having an emitter, a base, and a collector, the emitter of the third transistor being connected to the supply voltage, the base of the third transistor being connected to the collector of the second transistor, the emitter of said fourth transistor being connected to the base of said second transistor and to the collector of the third transistor, the base of said fourth transistor being connected to receive said input voltage signal, and the collector of said fourth transistor being connected to the reference voltage, the emitter areas of the first and second transistors being sized to match the base to emitter voltages of said first and second transistors, and the emitter areas of the third and fourth transistors being sized to match the base to emitter voltages of said third and fourth transistors, wherein a base-emitter voltage of the first transistor is applied across the base-emitter junction of the third transistor to provide said reference current through said second stage to maintain a voltage across the load that is substantially equal to the input voltage signal; and a startup transistor connected to one of said transistors of said second emitter-follower stage for starting the circuit when no load current is being drawn by driving a current into the load circuit, said startup transistor having an emitter, base, and collector, the emitter of said startup transistor being connected to the collector of said third transistor, the collector of said startup transistor being connected to the emitter of said third transistor, and the base of said startup transistor being connected to receive said input voltage signal.

Claim 21

A buffer circuit for connection between an input voltage signal and a load, comprising: a first emitter-follower stage for conducting a load current, said emitter-follower stage comprising a first and a second transistor, each having an emitter, a base, and a collector, said first transistor having its emitter connected to the collector of the second transistor, and being diode-connected with its collector and base interconnected to a supply voltage, and the emitter of said second transistor being connected to a node for connection to the load; a second emitter-follower stage through which a control current flows between the supply voltage and a reference potential, said second emitter-follower stage comprising a third and a fourth transistor, each having an emitter, a base, and a collector, the emitter of the third transistor being connected to the supply voltage, the base of the third transistor being connected to the collector of the second transistor, the emitter of said fourth transistor being connected to the base of said second transistor and to the collector of the third transistor, the base of said fourth transistor being connected to receive said input voltage signal, and the collector of said fourth transistor being connected to the reference voltage, the emitter areas of the first and second transistors being sized to match the base to emitter voltages of said first and second transistors, and the emitter areas of the third and fourth transistors being sized to match the base to emitter voltages of said third and fourth transistors, wherein a base-emitter voltage of the first transistor is applied across the base-emitter junction of the third transistor to provide said reference current through said second stage to maintain a voltage across the load that is substantially equal to the input voltage signal; and a startup transistor connected to one of said transistors of said second emitter-follower stage for starting the circuit when no load current is being drawn by driving a current into the load circuit, said startup transistor having an emitter, base, and collector, the emitter of said startup transistor being connected to the collector of said third transistor, the collector of said startup transistor being connected to the emitter of said third transistor, and the base of said startup transistor being connected to receive said input voltage signal.

Claim 22

A buffer circuit for connection between an input voltage signal and a load, comprising: a first emitter-follower stage for conducting a load current, said emitter-follower stage comprising a first and a second transistor, each having an emitter, a base, and a collector, said first transistor having its emitter connected to the collector of the second transistor, and being diode-connected with its collector and base interconnected to a supply voltage, and the emitter of said second transistor being connected to a node for connection to the load; a second emitter-follower stage through which a control current flows between the supply voltage and a reference potential, said second emitter-follower stage comprising a third and a fourth transistor, each having an emitter, a base, and a collector, the emitter of the third transistor being connected to the supply voltage, the base of the third transistor being connected to the collector of the second transistor, the emitter of said fourth transistor being connected to the base of said second transistor and to the collector of the third transistor, the base of said fourth transistor being connected to receive said input voltage signal, and the collector of said fourth transistor being connected to the reference voltage; wherein a base-emitter voltage of the first transistor is applied across the base-emitter junction of the third transistor to provide said reference current through said second stage to maintain a voltage across the load that has a fixed relationship to the input voltage signal; and first and second resistors of substantially equal value, said first and second resistors being connected, respectively, between the emitter of said fourth transistor and the collector of the third transistor, and from the emitter of said third transistor to the supply voltage to maintain the V BE of said second transistor substantially equal to the V BE of said fourth transistor.

Claim 23

A buffer circuit for connection between an input voltage signal and a load, comprising: a first emitter-follower stage for conducting a load current, said emitter-follower stage comprising a first and a second transistor, each having an emitter, a base, and a collector, said first transistor having its emitter connected to the collector of the second transistor, and being diode-connected with its collector and base interconnected to a supply voltage, and the emitter of said second transistor being connected to a node for connection to the load; a second emitter-follower stage through which a control current flows between the supply voltage and a reference potential, said second emitter-follower stage comprising a third and a fourth transistor, each having an emitter, a base, and a collector, the emitter of the third transistor being connected to the supply voltage, the base of the third transistor being connected to the collector of the second transistor, the emitter of said fourth transistor being connected to the base of said second transistor and to the collector of the third transistor, the base of said fourth transistor being connected to receive said input voltage signal, and the collector of said fourth transistor being connected to the reference voltage; wherein a base-emitter voltage of the first transistor is applied across the base-emitter junction of the third transistor to provide said reference current through said second stage to maintain a voltage across the load that has a fixed relationship to the input voltage signal; and first and second resistors of substantially equal value, said first and second resistors being connected, respectively, between the emitter of said fourth transistor and the collector of the third transistor, and from the emitter of said third transistor to the supply voltage to maintain the V BE of said second transistor substantially equal to the V BE of said fourth transistor.

Claim 24

A buffer circuit for connection between an input voltage signal and a load, comprising: a first emitter-follower stage for conducting a load current, said emitter-follower stage comprising a first and a second transistor, each having an emitter, a base, and a collector, said first transistor having its emitter connected to the collector of the second transistor, and being diode-connected with its collector and base interconnected to a supply voltage, and the emitter of said second transistor being connected to a node for connection to the load; a second emitter-follower stage through which a control current flows between the supply voltage and a reference potential, said second emitter-follower stage comprising a third and a fourth transistor, each having an emitter, a base, and a collector, the emitter of the third transistor being connected to the supply voltage, the base of the third transistor being connected to the collector of the second transistor, the emitter of said fourth transistor being connected to the base of said second transistor and to the collector of the third transistor, the base of said fourth transistor being connected to receive said input voltage signal, and the collector of said fourth transistor being connected to the reference voltage; wherein a base-emitter voltage of the first transistor is applied across the base-emitter junction of the third transistor to provide said reference current through said second stage to maintain a voltage across the load that has a fixed relationship to the input voltage signal; and a pass transistor having an emitter, a base, and a collector, said pass transistor being in series with the second transistor, said pass transistor having its base current mirrored into the base of said second transistor to obtain a first order compensation of the base current of said second transistor.

Claim 25

A buffer circuit for connection between an input voltage signal and a load, comprising: a first emitter-follower stage for conducting a load current, said emitter-follower stage comprising a first and a second transistor, each having an emitter, a base, and a collector, said first transistor having its emitter connected to the collector of the second transistor, and being diode-connected with its collector and base interconnected to a supply voltage, and the emitter of said second transistor being connected to a node for connection to the load; a second emitter-follower stage through which a control current flows between the supply voltage and a reference potential, said second emitter-follower stage comprising a third and a fourth transistor, each having an emitter, a base, and a collector, the emitter of the third transistor being connected to the supply voltage, the base of the third transistor being connected to the collector of the second transistor, the emitter of said fourth transistor being connected to the base of said second transistor and to the collector of the third transistor, the base of said fourth transistor being connected to receive said input voltage signal, and the collector of said fourth transistor being connected to the reference voltage; wherein a base-emitter voltage of the first transistor is applied across the base-emitter junction of the third transistor to provide said reference current through said second stage to maintain a voltage across the load that has a fixed relationship to the input voltage signal; and a pass transistor having an emitter, a base, and a collector, said pass transistor being in series with the second transistor, said pass transistor having its base current mirrored into the base of said second transistor to obtain a first order compensation of the base current of said second transistor.

Claim 26

A buffer circuit for connection between an input voltage signal and a load, comprising: a first emitter-follower stage for conducting a load current, said emitter-follower stage comprising a first and a second transistor, each having an emitter, a base, and a collector, said first transistor having its emitter connected to the collector of the second transistor, and being diode-connected with its collector and base interconnected to a supply voltage, and the emitter of said second transistor being connected to a node for connection to the load; a second emitter-follower stage through which a control current flows between the supply voltage and a reference potential, said second emitter-follower stage comprising a third and a fourth transistor, each having an emitter, a base, and a collector, the emitter of the third transistor being connected to the supply voltage, the base of the third transistor being connected to the collector of the second transistor, the emitter of said fourth transistor being connected to the base of said second transistor and to the collector of the third transistor, the base of said fourth transistor being connected to receive said input voltage signal, and the collector of said fourth transistor being connected to the reference voltage, the emitter areas of the first and second transistors being substantially equal, and the emitter areas of the third and fourth transistors being substantially equal; wherein a base-emitter voltage of the first transistor is applied across the base-emitter junction of the third transistor to provide said reference current through said second stage to maintain a voltage across the load that is substantially equal to the input voltage signal; and a startup transistor connected to one of said transistors of said second emitter-follower stage for starting the circuit when no load current is being drawn by driving a current into the load circuit, said startup transistor having an emitter, base, and collector, the emitter and base being connected respectively to the emitter and base of said fourth transistor, and the collector being connected to said supply voltage.

Claim 27

A buffer circuit for connection between an input voltage signal and a load, comprising: a first emitter-follower stage for conducting a load current, said emitter-follower stage comprising a first and a second transistor, each having an emitter, a base, and a collector, said first transistor having its emitter connected to the collector of the second transistor, and being diode-connected with its collector and base interconnected to a supply voltage, and the emitter of said second transistor being connected to a node for connection to the load; a second emitter-follower stage through which a control current flows between the supply voltage and a reference potential, said second emitter-follower stage comprising a third and a fourth transistor, each having an emitter, a base, and a collector, the emitter of the third transistor being connected to the supply voltage, the base of the third transistor being connected to the collector of the second transistor, the emitter of said fourth transistor being connected to the base of said second transistor and to the collector of the third transistor, the base of said fourth transistor being connected to receive said input voltage signal, and the collector of said fourth transistor being connected to the reference voltage, the emitter areas of the first and second transistors being substantially equal, and the emitter areas of the third and fourth transistors being substantially equal; wherein a base-emitter voltage of the first transistor is applied across the base-emitter junction of the third transistor to provide said reference current through said second stage to maintain a voltage across the load that is substantially equal to the input voltage signal; and a startup transistor connected to one of said transistors of said second emitter-follower stage for starting the circuit when no load current is being drawn by driving a current into the load circuit, said startup transistor having an emitter, base, and collector, the emitter and base being connected respectively to the emitter and base of said fourth transistor, and the collector being connected to said supply voltage.

Claim 28

A buffer circuit for connection between an input voltage signal and a load, comprising: a first emitter-follower stage for conducting a load current, said emitter-follower stage comprising a first and a second transistor, each having an emitter, a base, and a collector, said first transistor having its emitter connected to the collector of the second transistor, and being diode-connected with its collector and base interconnected to a supply voltage, and the emitter of said second transistor being connected to a node for connection to the load; a second emitter-follower stage through which a control current flows between the supply voltage and a reference potential, said second emitter-follower stage comprising a third and a fourth transistor, each having an emitter, a base, and a collector, the emitter of the third transistor being connected to the supply voltage, the base of the third transistor being connected to the collector of the second transistor, the emitter of said fourth transistor being connected to the base of said second transistor and to the collector of the third transistor, the base of said fourth transistor being connected to receive said input voltage signal, and the collector of said fourth transistor being connected to the reference voltage; wherein a base-emitter voltage of the first transistor is applied across the base-emitter junction of the third transistor to provide said reference current through said second stage to maintain a voltage across the load that has a fixed relationship to the input voltage signal; and first and second resistors of substantially equal value, said first and second resistors being connected, respectively, between the emitter of said first transistor and the collector of the second transistor, and from the emitter of said second transistor to the load connection node to maintain the V BE of said second transistor substantially equal to the V BE of said fourth transistor.

Claim 29

A buffer circuit for connection between an input voltage signal and a load, comprising: a first emitter-follower stage for conducting a load current, said emitter-follower stage comprising a first and a second transistor, each having an emitter, a base, and a collector, said first transistor having its emitter connected to the collector of the second transistor, and being diode-connected with its collector and base interconnected to a supply voltage, and the emitter of said second transistor being connected to a node for connection to the load; a second emitter-follower stage through which a control current flows between the supply voltage and a reference potential, said second emitter-follower stage comprising a third and a fourth transistor, each having an emitter, a base, and a collector, the emitter of the third transistor being connected to the supply voltage, the base of the third transistor being connected to the collector of the second transistor, the emitter of said fourth transistor being connected to the base of said second transistor and to the collector of the third transistor, the base of said fourth transistor being connected to receive said input voltage signal, and the collector of said fourth transistor being connected to the reference voltage; wherein a base-emitter voltage of the first transistor is applied across the base-emitter junction of the third transistor to provide said reference current through said second stage to maintain a voltage across the load that has a fixed relationship to the input voltage signal; and first and second resistors of substantially equal value, said first and second resistors being connected, respectively, between the emitter of said first transistor and the collector of the second transistor, and from the emitter of said second transistor to the load connection node to maintain the V BE of said second transistor substantially equal to the V BE of said fourth transistor.