US5124586A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Impedance multiplier
Assignee: STMicroelectronics lnc USA
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Filing: 1991-08-16
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Granted: 1992-06-23
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Expires: 2011-08-16
Abstract
Abstract A circuit for presenting a multiplied impedance at in input node includes a resistor having a value desired to be multiplied at the input node connected at one end to a reference potential. A first transistor has a current path in series between the input node and the other end of the resistor. A voltage divider is connected at one end to the reference potential, and a second transistor has a current path in series between a voltage source and the other end of the voltage divider, so that the second transistor and the voltage divider form an emitter follower circuit, to provide feedback to said first transistor circuit. A current control element of the first transistor is connected to receive the divided voltage from the voltage divider, and a current control element of the second transistor being connected to the input node. The transistors can be either bipolar, enhancement FET or MOS enhancement FET type devices.
Inventors
- 👤 Francesco Carobolante
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:17
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/02; H03H11/40; H03H11/405
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
279 words
A circuit for presenting an equivalent resistance, at an input node, representing a multiplied resistance comprising: a first resistor, R 1 , having a value desired to be multiplied at said input node for voltages on said input node in a range below a voltage source, said first resistor being connected at one end to a reference voltage; a first transistor of first conductivity type connected in series between said input node and another end of said first resistor; a first voltage divider connected at one end to said reference voltage; a second transistor of said first conductivity type connected in series between said voltage source and another end of said first voltage divider; a control terminal of said first transistor being connected to receive a divided voltage from said first voltage divider; a control terminal of said second transistor being connected to said input node; a second resistor, R 2 , having a value desired to be multiplied at said input node for voltages on said input node in a range above said reference voltage source, said second resistor being connected at one end to said voltage source; a third transistor of second conductivity type connected in series between said input node and another end of said second resistor; a second voltage divider connected at one end to said voltage source; a fourth transistor of said second conductivity type connected in series between said reference voltage and another end of said second voltage divider; a control terminal of said third transistor being connected to receive a divided voltage from said second voltage divider; and a current control terminal of said fourth transistor being connected to said input node.
Claim 2
Dependent Claim
279 words
A circuit for presenting an equivalent resistance, at an input node, representing a multiplied resistance comprising: a first resistor, R 1 , having a value desired to be multiplied at said input node for voltages on said input node in a range below a voltage source, said first resistor being connected at one end to a reference voltage; a first transistor of first conductivity type connected in series between said input node and another end of said first resistor; a first voltage divider connected at one end to said reference voltage; a second transistor of said first conductivity type connected in series between said voltage source and another end of said first voltage divider; a control terminal of said first transistor being connected to receive a divided voltage from said first voltage divider; a control terminal of said second transistor being connected to said input node; a second resistor, R 2 , having a value desired to be multiplied at said input node for voltages on said input node in a range above said reference voltage source, said second resistor being connected at one end to said voltage source; a third transistor of second conductivity type connected in series between said input node and another end of said second resistor; a second voltage divider connected at one end to said voltage source; a fourth transistor of said second conductivity type connected in series between said reference voltage and another end of said second voltage divider; a control terminal of said third transistor being connected to receive a divided voltage from said second voltage divider; and a current control terminal of said fourth transistor being connected to said input node.
Claim 3
Dependent Claim
11 words
The circuit of claim 1 wherein said transistors are bipolar transistors.
Claim 4
Dependent Claim
23 words
The circuit of claim 2 wherein said first and second transistors are NPN transistors, and said third and fourth transistors are PNP transistors.
Claim 5
Dependent Claim
37 words
The circuit of claim 1 wherein said first voltage divider comprises third and fourth resistors R 3 and R 4 , and said second voltage divider is fifth and sixth resistors R 5 and R 6 .
Claim 6
Dependent Claim
41 words
The circuit of claim 4 wherein the first and second resistors are equal, the third and fifth resistors are equal, and the fourth and sixth resistors are equal, whereby the impedance at said input node is: Z.sub.IN =R.sub.1 X (R.sub.3 +R.sub.4)/2R.sub.3.
Claim 7
Dependent Claim
221 words
A circuit for providing a load impedance at an input node representing a multiplied impedance comprising: a first impedance having a value desired to be multiplied to provide said load impedance, said first impedance being connected at one end to a reference voltage; a first transistor connected between said input node and another end of said first impedance; a first voltage divider connected at one end to said reference voltage; a second transistor connected between a voltage source and another end of said first voltage divider; a control terminal of said first transistor being connected to receive a divided voltage from said first voltage divider; a control terminal of said second transistor being connected to said input node; a second impedance having a value desired to be multiplied to provide said load impedance, said second impedance being connected at one end to said voltage source; a third transistor connected between said input node and another end of said second impedance; a second voltage divider connected at one end to said voltage source; a fourth transistor connected between said reference voltage and another end of said second voltage divider; a control terminal of said third transistor being connected to receive a divided voltage from said second voltage divider; and a control terminal of said fourth transistor being connected to said input node.
Claim 8
Dependent Claim
221 words
A circuit for providing a load impedance at an input node representing a multiplied impedance comprising: a first impedance having a value desired to be multiplied to provide said load impedance, said first impedance being connected at one end to a reference voltage; a first transistor connected between said input node and another end of said first impedance; a first voltage divider connected at one end to said reference voltage; a second transistor connected between a voltage source and another end of said first voltage divider; a control terminal of said first transistor being connected to receive a divided voltage from said first voltage divider; a control terminal of said second transistor being connected to said input node; a second impedance having a value desired to be multiplied to provide said load impedance, said second impedance being connected at one end to said voltage source; a third transistor connected between said input node and another end of said second impedance; a second voltage divider connected at one end to said voltage source; a fourth transistor connected between said reference voltage and another end of said second voltage divider; a control terminal of said third transistor being connected to receive a divided voltage from said second voltage divider; and a control terminal of said fourth transistor being connected to said input node.
Claim 9
Dependent Claim
16 words
The circuit of claim 6 wherein said first, second, third and fourth transistors are bipolar transistors.
Claim 10
Dependent Claim
23 words
The circuit of claim 7 wherein said first and second transistors are PNP transistors, and said third and fourth transistors are NPN transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-23 | 1995-12-23 | 1996-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-23 | 1999-12-23 | 2000-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-23 | 2003-12-23 | 2004-06-23 | $7700.00 | Window Closed / Lapsed |