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US4517508A Expired / Lapsed US ⏱️ 0.0 years remaining

Variable impedance circuit

Assignee: Toko Inc
•
Filing: 1983-05-03
•
Granted: 1985-05-14
•
Expires: 2003-05-03
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Abstract

Abstract A variable impedance circuit is disclosed which comprises a pair of diodes having their cathodes connected together, a first current source coupled to the connection between the diodes, and a second and a third current source which are connected to the anodes of the diodes respectively. The second and third current sources are controlled by means of current mirror circuits so that equal forward currents are caused to flow therefrom to the paired diodes, thus making it possible to set up a desired impedance variation range.

Inventors

  • 👤 Koichi Sakai

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 08:20
CPC Classifications
H; H03; H03G; H03G1/00; H03G1/0005; H03G1/0035; H03G1/0052

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 207 words
A variable impedance circuit, comprising: a pair of diodes connected with each other; a first current source circuit coupled to the connection point between said diodes; a second and a third current source circuit connected to the anodes of said diodes respectively; terminals provided at the anode sides of said diodes respectively so that a variable impedance element is established therebetween; a first current mirror circuit for equally controlling forward currents flowing from said second and third current source circuits to said diodes respectively; a second current mirror circuit for flowing, through said first current source circuit, a current substantially equal to the sum of the forward currents flowing out of said second and third current source circuits; a transistor driven with a control voltage higher than a predetermined level to draw in a current from said first current mirror circuit; and a third current mirror circuit driven with a control voltage lower than a predetermined level to draw in a current from said first current mirror circuit; wherein currents derived from said transistor and said third current mirror circuit are caused to flow, through said first current mirror circuit, in said pair of diodes as equal forward currents, thereby making variable the impedance between said terminals.
Claim 2
Dependent Claim 207 words
A variable impedance circuit, comprising: a pair of diodes connected with each other; a first current source circuit coupled to the connection point between said diodes; a second and a third current source circuit connected to the anodes of said diodes respectively; terminals provided at the anode sides of said diodes respectively so that a variable impedance element is established therebetween; a first current mirror circuit for equally controlling forward currents flowing from said second and third current source circuits to said diodes respectively; a second current mirror circuit for flowing, through said first current source circuit, a current substantially equal to the sum of the forward currents flowing out of said second and third current source circuits; a transistor driven with a control voltage higher than a predetermined level to draw in a current from said first current mirror circuit; and a third current mirror circuit driven with a control voltage lower than a predetermined level to draw in a current from said first current mirror circuit; wherein currents derived from said transistor and said third current mirror circuit are caused to flow, through said first current mirror circuit, in said pair of diodes as equal forward currents, thereby making variable the impedance between said terminals.
Claim 3
Dependent Claim 18 words
A variable impedance circuit according to claim 1, wherein said pair of diodes are constituted by diode-connected transistors.

References Cited (Backward Citations)

DE2350718A1 Cited
DE2517174A1 Cited
US4066914A Cited
US4220875A Cited
US4179650A Cited
JPS54121044A Cited
US4288707A Cited
US4339677A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-05-13 1988-11-12 1989-05-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-05-13 1992-11-12 1993-05-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-05-13 1996-11-12 1997-05-14 $7700.00 Window Closed / Lapsed

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