Patent US5245212A successfully refreshed from Google Patents.
US5245212A
Expired / Lapsed
US
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Self-aligned field-plate isolation between active elements
Assignee: Texas Instruments Inc
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Filing: 1991-11-04
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Granted: 1993-09-14
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Expires: 2011-11-04
Abstract
Abstract The structure and method of this invention provide, for example, electrical isolation between active elements in adjacent rows and/or columns of an integrated circuit by use of a self-aligned field-plate conductor formed over and insulated from the substrate regions that are bounded by the channel regions of field-effect transistors in adjacent rows and that are bounded by the bitlines forming those transistors in a column. The field-plate conductor is formed, for example, in a strip that extends over the isolation areas and thermal insulator regions between row lines of the memory cell array. The field-plate conductor strip is connected to a voltage supply that has a potential with respect to the potential of the semiconductor substrate which causes the isolation areas to be nonconductive. Component density may be increased over that of prior-art structures and methods.
Inventors
- 👤 Manzur Gill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:13
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/111; H10B; H10B69/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
95 words
An isolating structure between control electrodes of active elements of an integrated circuit, each of said control electrodes having at least one edge and having a sidewall insulator adjacent said edge, comprising: a semiconductor substrate region between a said edge of a said control electrode and a said edge of an adjacent said control electrode; an insulator layer overlying said semiconductor substrate region; and a field-plate conductor overlying said insulator layer and abutting said sidewall insulator, said field-plate conductor electrically insulated from at least a said edge of said control electrode by said sidewall insulator.
Claim 2
Dependent Claim
95 words
An isolating structure between control electrodes of active elements of an integrated circuit, each of said control electrodes having at least one edge and having a sidewall insulator adjacent said edge, comprising: a semiconductor substrate region between a said edge of a said control electrode and a said edge of an adjacent said control electrode; an insulator layer overlying said semiconductor substrate region; and a field-plate conductor overlying said insulator layer and abutting said sidewall insulator, said field-plate conductor electrically insulated from at least a said edge of said control electrode by said sidewall insulator.
Claim 3
Dependent Claim
83 words
An isolating structure between control electrodes of active elements of memory cells in an array of said cells, said control electrodes having sidewall insulators, comprising: a semiconductor layer between said control electrodes; a field-plate formed over and insulated from said semiconductor layer, insulated from said control electrodes by said sidewall insulators, and abutting said sidewall insulators; said field-plate connected to a source of electric potential that, in relation to the electric potential of said semiconductor layer, causes said semiconductor layer to be nonconductive.
Claim 4
Dependent Claim
83 words
An isolating structure between control electrodes of active elements of memory cells in an array of said cells, said control electrodes having sidewall insulators, comprising: a semiconductor layer between said control electrodes; a field-plate formed over and insulated from said semiconductor layer, insulated from said control electrodes by said sidewall insulators, and abutting said sidewall insulators; said field-plate connected to a source of electric potential that, in relation to the electric potential of said semiconductor layer, causes said semiconductor layer to be nonconductive.
Claim 5
Dependent Claim
90 words
A nonvolatile memory array comprising rows and columns of active elements formed on the surface of said semiconductor layer, each said element having a control electrode defining a channel region in said surface, said control electrode having adjacent sidewall insulators, said channel region spaced apart by a semiconductor region from a channel region of a said active element of an adjacent row, including: a field-plate formed over and insulated from said semiconductor region, said field-plate abutting said sidewall insulators and electrically insulated from said control electrodes by said sidewall insulators.
Claim 6
Dependent Claim
90 words
A nonvolatile memory array comprising rows and columns of active elements formed on the surface of said semiconductor layer, each said element having a control electrode defining a channel region in said surface, said control electrode having adjacent sidewall insulators, said channel region spaced apart by a semiconductor region from a channel region of a said active element of an adjacent row, including: a field-plate formed over and insulated from said semiconductor region, said field-plate abutting said sidewall insulators and electrically insulated from said control electrodes by said sidewall insulators.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-09-13 | 1997-03-15 | 1997-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-13 | 2001-03-15 | 2001-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-13 | 2005-03-15 | 2005-09-14 | $7700.00 | Window Closed / Lapsed |