US5243576A — Semiconductor memory device

Claim 1

Independent Claim 188 words

A semiconductor memory device comprising a frequency divider for selectively dividing clock pulses in accordance with frequency-division control pulses to output frequency-divided pulses; a frequency-division control circuit for, upon reaching a specified count while counting said clock pulses in response to a control pulse input, changing said frequency-division control pulses; refresh-address generating means for generating a refresh address each time said refresh-address generating means receives a pulse; a refresh control circuit for generating a word-line activating pulse each time said refresh control circuit receives a pulse; a memory cell array including a plurality of memory cells each connected to one of a plurality of word lines and one of a plurality of bit lines; decoder means for selecting one of said word lines in accordance with said refresh address and activating the selected one of said word lines in response to said word-line activating pulse; and a selector for, in response to said control pulse input, selecting one of said frequency-divided pulses and said refresh pulses and supplying the selected one of said frequency-divided pulses and refresh pulses to said refresh-address generating means and said refresh control circuit.

Claim 2

Dependent Claim 188 words

A semiconductor memory device comprising a frequency divider for selectively dividing clock pulses in accordance with frequency-division control pulses to output frequency-divided pulses; a frequency-division control circuit for, upon reaching a specified count while counting said clock pulses in response to a control pulse input, changing said frequency-division control pulses; refresh-address generating means for generating a refresh address each time said refresh-address generating means receives a pulse; a refresh control circuit for generating a word-line activating pulse each time said refresh control circuit receives a pulse; a memory cell array including a plurality of memory cells each connected to one of a plurality of word lines and one of a plurality of bit lines; decoder means for selecting one of said word lines in accordance with said refresh address and activating the selected one of said word lines in response to said word-line activating pulse; and a selector for, in response to said control pulse input, selecting one of said frequency-divided pulses and said refresh pulses and supplying the selected one of said frequency-divided pulses and refresh pulses to said refresh-address generating means and said refresh control circuit.

Claim 3

Dependent Claim 38 words

A semiconductor memory device according to claim 1, wherein said frequency divider circuit comprises division means including a plurality of flip-flops and means for controlling the outputs of said frequency-divider circuit in accordance with said frequency-division control pulses.

Claim 4

Dependent Claim 52 words

A semiconductor memory device according to claim 1, wherein said frequency-division controller circuit comprises counting means for, upon reaching a specified count while counting said clock pulses in response to said control pulse, generating a detection pulse; and control means for changing said frequency-division control pulses in response to said detection pulse.

Claim 5

Dependent Claim 35 words

A semiconductor memory device according to claim 1, wherein said frequency-division controller circuit comprises means for changing said frequency-division control pulse in response to a detection signal from a counter constituting said address generating means.

Claim 6

Dependent Claim 92 words

A semiconductor memory device comprising a memory cell array including a plurality of memory cells, refresh timing control means activated in a self-refresh mode for generating a refresh timing signal having a first cycle period, a refresh control circuit performing a refresh operation on said memory cells each time said first refresh timing signal is generated, and timing changing means for changing a cycle period of said refresh timing signal from said first cycle period to a second cycle period after a predetermined number of said refresh timing signals having been generated.

Claim 7

Dependent Claim 92 words

A semiconductor memory device comprising a memory cell array including a plurality of memory cells, refresh timing control means activated in a self-refresh mode for generating a refresh timing signal having a first cycle period, a refresh control circuit performing a refresh operation on said memory cells each time said first refresh timing signal is generated, and timing changing means for changing a cycle period of said refresh timing signal from said first cycle period to a second cycle period after a predetermined number of said refresh timing signals having been generated.

Claim 8

Dependent Claim 20 words

The memory device as claimed in claim 5, wherein said first cycle period is shorter than said second cycle period.

Claim 9

Dependent Claim 115 words

The memory device as claimed in claim 5, further comprising: receiving means for receiving a refresh pulse signal in an operation mode other than said self-refresh mode; and selector means coupled to said receiving means and said refresh timing control means for selecting said refresh pulse signal in an operation mode which is different from said self-refresh mode and selecting said refresh timing signal in said self-refresh mode and supplying the selected one of said refresh pulse signal and said refresh timing signal to said refresh control circuit, said refresh control circuit responding to either one of said refresh pulse signal and said refresh timing signal to perform said refresh operation on said memory cells.

Claim 10

Dependent Claim 192 words

A semiconductor memory device comprising a memory cell array including a plurality of word lines, a plurality of bit lines and a plurality of memory cells each coupled to one of said word lines and one of said bit lines, means receiving a control signal, said semiconductor memory device being brought into a self-refresh mode by said receiving means in response to an active level of said control signal, a refresh control circuit activating at least one of said word lines to perform a refresh operation on said memory cells each time a refresh timing signal is supplied thereto, a timing circuit responding to said active level of said control signal to generate a refresh timing pulse at a first cycle period, supplying means for supplying said refresh timing pulse to said refresh control circuit as said refresh timing signal, and means for causing said timing circuit to change a cycle period of said timing pulse from said first cycle period to a second cycle period after all of said word lines are activated to refresh all of said memory cells, said first cycle period being different from said second cycle period.

Claim 11

Dependent Claim 192 words

A semiconductor memory device comprising a memory cell array including a plurality of word lines, a plurality of bit lines and a plurality of memory cells each coupled to one of said word lines and one of said bit lines, means receiving a control signal, said semiconductor memory device being brought into a self-refresh mode by said receiving means in response to an active level of said control signal, a refresh control circuit activating at least one of said word lines to perform a refresh operation on said memory cells each time a refresh timing signal is supplied thereto, a timing circuit responding to said active level of said control signal to generate a refresh timing pulse at a first cycle period, supplying means for supplying said refresh timing pulse to said refresh control circuit as said refresh timing signal, and means for causing said timing circuit to change a cycle period of said timing pulse from said first cycle period to a second cycle period after all of said word lines are activated to refresh all of said memory cells, said first cycle period being different from said second cycle period.

Claim 12

Dependent Claim 20 words

The memory device as claimed in claim 8, wherein said first cycle period is shorter than said second cycle period.

Claim 13

Dependent Claim 88 words

The memory device as claimed in claim 9, said supplying means comprises: receiving means for receiving a refresh control pulse; and a selector coupled to said refresh control pulse receiving means and said timing circuit for selecting and supplying said timing pulse to said refresh control circuit as said refresh timing signal when said control signal is at said active level and selecting and supplying said refresh control pulse to said refresh control circuit as said refresh timing signal when said control signal is at an inactive level.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1996-09-06	1997-03-08	1997-09-07	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2000-09-06	2001-03-08	2001-09-07	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2004-09-06	2005-03-08	2005-09-07	$7700.00	Window Closed / Lapsed

Semiconductor memory device

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