Patent US5243456A successfully refreshed from Google Patents.
US5243456A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Sumitomo Electric Industries Ltd
•
Filing: 1991-07-03
•
Granted: 1993-09-07
•
Expires: 2011-07-03
Abstract
Abstract A semiconductor device for driving a light emitting element used in high speed optical communication. The semiconductor device comprises circuitry for delaying a clock signal and producing first and second delay signals. The second delay signal has a delay time different from that of the first delay signal. The first delay signal controls flip-flop circuitry which receives a data signal and outputs a signal indicative of the data signal. The first delay signal also controls a first latch circuit to receive the signal from the flip-flop circuitry and output a signal with the delay time of the first delay signal. The second delay signal controls a second latch circuit to receive the signal from the flip-flop circuitry and output a signal with the delay time of the second delay signal. The signals output from the first and second latch circuits are logically combined by logic circuitry. The logic circuitry is either AND or OR circuitry. The logic circuitry outputs the result of the combination to driving circuitry which provides the current to drive the light emitting element in accordance with the output of the logic circuitry.
Inventors
- 👤 Noriyuki Hirakata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:42
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/04; H03K5/05
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
250 words
A semiconductor device comprising: means for delaying a clock signal and providing a first delay signal and a second delay signal independent of said first delay signal in accordance with said clock signal, said first and second delay signals having predetermined delay times different from each other; flip-flop circuit means, coupled to said delaying means, for receiving a data signal and outputting a first signal indicative thereof, said receiving and outputting being controlled by said first delay signal; first latch circuit means, coupled to said flip-flop circuit means and said delaying means , for receiving said first signal and outputting a second signal indicative of said first signal, said second signal having a delay time in accordance with said early time of said first delay signal; second latch circuit means, coupled to said flip-flop circuit means and said delaying means, for receiving said first signal and outputting a third signal indicative of said first signal, said third signal having a delay time in accordance with said delay time of said second delay signal; logic means, coupled to said first and second latch circuit means, for logically combining said second and third signals and providing a fourth logically combined signal in accordance therewith, said fourth logically combined signal always having at least one low level and one high level; means for emitting a light signal; and means, coupled to said logic means and said light signal emitting means, for driving said light signal emitting means in accordance with said fourth signal.
Claim 2
Dependent Claim
250 words
A semiconductor device comprising: means for delaying a clock signal and providing a first delay signal and a second delay signal independent of said first delay signal in accordance with said clock signal, said first and second delay signals having predetermined delay times different from each other; flip-flop circuit means, coupled to said delaying means, for receiving a data signal and outputting a first signal indicative thereof, said receiving and outputting being controlled by said first delay signal; first latch circuit means, coupled to said flip-flop circuit means and said delaying means , for receiving said first signal and outputting a second signal indicative of said first signal, said second signal having a delay time in accordance with said early time of said first delay signal; second latch circuit means, coupled to said flip-flop circuit means and said delaying means, for receiving said first signal and outputting a third signal indicative of said first signal, said third signal having a delay time in accordance with said delay time of said second delay signal; logic means, coupled to said first and second latch circuit means, for logically combining said second and third signals and providing a fourth logically combined signal in accordance therewith, said fourth logically combined signal always having at least one low level and one high level; means for emitting a light signal; and means, coupled to said logic means and said light signal emitting means, for driving said light signal emitting means in accordance with said fourth signal.
Claim 3
Dependent Claim
15 words
A semiconductor device according to claim 1, wherein said logic means comprises an OR circuit.
Claim 4
Dependent Claim
15 words
A semiconductor device according to claim 1, wherein said logic means comprises an AND circuit.
Claim 5
Dependent Claim
26 words
A semiconductor device according to claim 1, wherein said delaying means comprises first and second delay circuits for providing said first and second delay signals, respectively.
Claim 6
Dependent Claim
20 words
A semiconductor device according to claim 4, wherein each of said delay circuits comprises one source coupled FET logic circuit.
Claim 7
Dependent Claim
22 words
A semiconductor device according to claim 4, wherein each of said delay circuits comprises a plurality of source coupled FET logic circuits.
Claim 8
Dependent Claim
19 words
A semiconductor device according to claim 5, wherein said source coupled FET logic circuit comprises a source follower circuit.
Claim 9
Dependent Claim
21 words
A semiconductor device according to claim 5, wherein said source coupled FET logic circuit comprises a plurality of source follower circuits.
References Cited (Backward Citations)
US4955081A
Cited
US4754164A
Cited
US4694196A
Cited
US4757214A
Cited
US4760291A
Cited
US4914326A
Cited
US4929850A
Cited
US4970405A
Cited
US4945262A
Cited
US5057722A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-09-06 | 1997-03-08 | 1997-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-06 | 2001-03-08 | 2001-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-06 | 2005-03-08 | 2005-09-07 | $7700.00 | Window Closed / Lapsed |