Patent US4494971A successfully refreshed from Google Patents.
Patent US5243236A successfully refreshed from Google Patents.
US5243236A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High voltage CMOS switch with protection against diffusion to well reverse junction breakdown
Assignee: Intel Corp
•
Filing: 1991-12-31
•
Granted: 1993-09-07
•
Expires: 2011-12-31
Abstract
Abstract A high voltage CMOS n-well switch with guarding against reverse junction breakdown, as well as gate-aided breakdown. The CMOS switch of the present invention comprises two pairs of cascoding p-channel MOSFET loads, two pairs of cascoding n-channel MOSFET drivers and an inverter for input. One device in each pair of MOSFETs is used as a guard against gate-aided breakdown. The p-channel MOSFETs have independent n-wells so that the guard devices have their n-wells independently biased without being pulled by the n-wells of the load devices. The inverter is used to provide complementary inputs to the switch. By having independent n-wells, the breakdown voltage of the switch is raised above p+/n-well reverse breakdown voltage.
Inventors
- 👤 Bart R. McDaniel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:56
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/08; H03K17/081; H03K17/08104; H03K17/10; H03K17/102; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356104; H03K3/356113
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
288 words
A CMOS n-well switch for providing level shifting in response to an input voltage, comprising: first and second p-channel MOSFETs with independent n-wells, the source and n-well of said first p-channel MOSFET being coupled to a first predetermined voltage, the gate of said first p-channel MOSFET forming a first node, the source and n-well of said second p-channel MOSFET being coupled to the drain of said first p-channel MOSFET, the drain of said second p-channel MOSFET forming a second node; third and fourth p-channel MOSFETs with independent n-wells, the source and n-well of said third p-channel MOSFET being coupled to said first predetermined voltage, the gate of said third p-channel MOSFET coupled to said second node, the source and n-well of said fourth p-channel MOSFET being coupled to the drain of said third p-channel MOSFET, the drain of said fourth p-channel MOSFET coupled to said first node, the gates of said second and fourth p-channel MOSFETs being coupled to a second predetermined voltage; an inverter coupled to convert said input voltage; first, second, third and fourth n-channel MOSFETs, said first and second being in cascode connection, said third and fourth being in cascode connection, said first n-channel MOSFET being coupled at its drain to said second p-channel MOSFET and to said second node, said third n-channel MOSFET being coupled at said first node to said fourth p-channel MOSFET and to the drain of said fourth n-channel MOSFET, the gates of said first and third n-channel MOSFETs being coupled to a third predetermined voltage, the gate of said fourth n-channel MOSFET being coupled to receive said input voltage, the gate of said second n-channel MOSFET being coupled to said inverter to receive the inverted input voltage from said inverter.
Claim 2
Dependent Claim
288 words
A CMOS n-well switch for providing level shifting in response to an input voltage, comprising: first and second p-channel MOSFETs with independent n-wells, the source and n-well of said first p-channel MOSFET being coupled to a first predetermined voltage, the gate of said first p-channel MOSFET forming a first node, the source and n-well of said second p-channel MOSFET being coupled to the drain of said first p-channel MOSFET, the drain of said second p-channel MOSFET forming a second node; third and fourth p-channel MOSFETs with independent n-wells, the source and n-well of said third p-channel MOSFET being coupled to said first predetermined voltage, the gate of said third p-channel MOSFET coupled to said second node, the source and n-well of said fourth p-channel MOSFET being coupled to the drain of said third p-channel MOSFET, the drain of said fourth p-channel MOSFET coupled to said first node, the gates of said second and fourth p-channel MOSFETs being coupled to a second predetermined voltage; an inverter coupled to convert said input voltage; first, second, third and fourth n-channel MOSFETs, said first and second being in cascode connection, said third and fourth being in cascode connection, said first n-channel MOSFET being coupled at its drain to said second p-channel MOSFET and to said second node, said third n-channel MOSFET being coupled at said first node to said fourth p-channel MOSFET and to the drain of said fourth n-channel MOSFET, the gates of said first and third n-channel MOSFETs being coupled to a third predetermined voltage, the gate of said fourth n-channel MOSFET being coupled to receive said input voltage, the gate of said second n-channel MOSFET being coupled to said inverter to receive the inverted input voltage from said inverter.
Claim 3
Dependent Claim
169 words
A CMOS n-well buffer inverter for inverting an input voltage with guarding devices against reverse junction breakdown, comprising: a first p-channel MOSFET having its n-well and source coupled to a first predetermined voltage, said first predetermined voltage being higher than said input voltage; a first n-channel MOSFET having its gate coupled to the gate of said first p-channel MOSFET to receive said input voltage; a second p-channel MOSFET having its source coupled with the drain of said first p-channel MOSFET, the n-well of said second p-channel MOSFET being coupled to the source of said second p-channel MOSFET, the gate of said second p-channel MOSFET being coupled to a second predetermined voltage biasing its gate; a second n-channel MOSFET having its drain coupled with the drain of said second p-channel MOSFET to form an output node, the gate of said second n-channel MOSFET being coupled to a third predetermined voltage biasing its gate, said drain of said first n-channel MOSFET being coupled with said source of said second n-channel MOSFET.
Claim 4
Dependent Claim
169 words
A CMOS n-well buffer inverter for inverting an input voltage with guarding devices against reverse junction breakdown, comprising: a first p-channel MOSFET having its n-well and source coupled to a first predetermined voltage, said first predetermined voltage being higher than said input voltage; a first n-channel MOSFET having its gate coupled to the gate of said first p-channel MOSFET to receive said input voltage; a second p-channel MOSFET having its source coupled with the drain of said first p-channel MOSFET, the n-well of said second p-channel MOSFET being coupled to the source of said second p-channel MOSFET, the gate of said second p-channel MOSFET being coupled to a second predetermined voltage biasing its gate; a second n-channel MOSFET having its drain coupled with the drain of said second p-channel MOSFET to form an output node, the gate of said second n-channel MOSFET being coupled to a third predetermined voltage biasing its gate, said drain of said first n-channel MOSFET being coupled with said source of said second n-channel MOSFET.
Claim 5
Dependent Claim
275 words
A CMOS p-well switch for providing level shifting in response to an input voltage, comprising: first, second, third and fourth p-channel MOSFETs, said first and second being in cascode connection such that the drain of said first p-channel MOSFET is coupled to the source of said second p-channel MOSFET, said third and fourth being in cascode connection such that the drain of said third p-channel MOSFET is coupled to the source of said fourth p-channel MOSFET, the gate of said first p-channel MOSFET being coupled to the drain of said fourth p-channel MOSFET to form an output node, the gate of said third p-channel MOSFET being coupled to the drain of said second p-channel MOSFET to form an inverted output node, the gates of said second and fourth p-channel MOSFETs being coupled to a first predetermined gate bias voltage; first and second cascoding n-channel MOSFETs with independent p-wells, the p-well of said first n-channel MOSFET being coupled to its source and to the drain of said second n-channel MOSFET, the gate of said first n-channel MOSFET being coupled to a second predetermined gate bias voltage; an inverter coupled to receive said input voltage and to generate an inverted input voltage; third and fourth cascoding n-channel MOSFETs with independent p-wells, the p-well of said third n-channel MOSFET being coupled to its source and to the drain of said fourth n-channel MOSFET, the gate of said third n-channel MOSFET being coupled to said second predetermined gate bias voltage, the gate of said second n-channel MOSFET being coupled to receive said input voltage, the gate of said fourth n-channel MOSFET being coupled to receive said inverted input voltage.
Claim 6
Dependent Claim
275 words
A CMOS p-well switch for providing level shifting in response to an input voltage, comprising: first, second, third and fourth p-channel MOSFETs, said first and second being in cascode connection such that the drain of said first p-channel MOSFET is coupled to the source of said second p-channel MOSFET, said third and fourth being in cascode connection such that the drain of said third p-channel MOSFET is coupled to the source of said fourth p-channel MOSFET, the gate of said first p-channel MOSFET being coupled to the drain of said fourth p-channel MOSFET to form an output node, the gate of said third p-channel MOSFET being coupled to the drain of said second p-channel MOSFET to form an inverted output node, the gates of said second and fourth p-channel MOSFETs being coupled to a first predetermined gate bias voltage; first and second cascoding n-channel MOSFETs with independent p-wells, the p-well of said first n-channel MOSFET being coupled to its source and to the drain of said second n-channel MOSFET, the gate of said first n-channel MOSFET being coupled to a second predetermined gate bias voltage; an inverter coupled to receive said input voltage and to generate an inverted input voltage; third and fourth cascoding n-channel MOSFETs with independent p-wells, the p-well of said third n-channel MOSFET being coupled to its source and to the drain of said fourth n-channel MOSFET, the gate of said third n-channel MOSFET being coupled to said second predetermined gate bias voltage, the gate of said second n-channel MOSFET being coupled to receive said input voltage, the gate of said fourth n-channel MOSFET being coupled to receive said inverted input voltage.
Claim 7
Dependent Claim
173 words
A CMOS p-well buffer inverter for inverting an input voltage with guarding devices against reverse junction breakdown, comprising: a first p-channel MOSFET having its source coupled to a first predetermined voltage, said first predetermined being higher than said input voltage; a first n-channel MOSFET having its gate coupled to the gate of said first p-channel MOSFET to receive said input voltage, said first n-channel MOSFET having its p-well and its source coupled to a second predetermined voltage; a second p-channel MOSFET having its source coupled with said first p-channel MOSFET at the drain of said first p-channel MOSFET, the gate of said second p-channel MOSFET being coupled to a third predetermined voltage biasing its gate; a second n-channel MOSFET having its drain coupled with the drain of said second p-channel MOSFET to form an output node, the gate of said second n-channel MOSFET being coupled to a fourth predetermined voltage biasing its gate, said second n-channel MOSFET having its p-well coupled to its source and to the drain of said first n-channel MOSFET.
Claim 8
Dependent Claim
173 words
A CMOS p-well buffer inverter for inverting an input voltage with guarding devices against reverse junction breakdown, comprising: a first p-channel MOSFET having its source coupled to a first predetermined voltage, said first predetermined being higher than said input voltage; a first n-channel MOSFET having its gate coupled to the gate of said first p-channel MOSFET to receive said input voltage, said first n-channel MOSFET having its p-well and its source coupled to a second predetermined voltage; a second p-channel MOSFET having its source coupled with said first p-channel MOSFET at the drain of said first p-channel MOSFET, the gate of said second p-channel MOSFET being coupled to a third predetermined voltage biasing its gate; a second n-channel MOSFET having its drain coupled with the drain of said second p-channel MOSFET to form an output node, the gate of said second n-channel MOSFET being coupled to a fourth predetermined voltage biasing its gate, said second n-channel MOSFET having its p-well coupled to its source and to the drain of said first n-channel MOSFET.
Claim 9
Dependent Claim
32 words
A CMOS n-well switch according to claim 1, wherein said first, second, third, and fourth n-channel MOSFETs are ratioed to be stronger devices than said first, second, third, and fourth p-channel MOSFETs.
Claim 10
Dependent Claim
28 words
A CMOS n-well buffer according to claim 2, wherein said first and second n-channel MOSFETs are ratioed to be stronger devices than said first and second p-channel MOSFETs.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-09-06 | 1997-03-08 | 1997-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-06 | 2001-03-08 | 2001-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-06 | 2005-03-08 | 2005-09-07 | $7700.00 | Window Closed / Lapsed |