Patent US5243228A successfully refreshed from Google Patents.
US5243228A
Expired / Lapsed
US
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Substrate bias voltage generator circuit
Assignee: Toshiba Corp
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Filing: 1992-04-08
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Granted: 1993-09-07
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Expires: 2012-04-08
Abstract
Abstract A substrate bias voltage generator circuit has a substrate bias voltage detector circuit, a substrate bias driver circuit, and a charge pump circuit. the substrate bias voltage detector circuit detects a substrate bias voltage applied to a semiconductor substrate and outputs a substrate bias voltage detection signal. The substrate bias detector circuit includes a P-channel transistor with a gate terminal and an N-channel transistor with a substrate terminal, both terminals being connected to the semiconductor substrate and the substrate bias voltage which is a back bias for the N-channel transistor. The substrate bias driver circuit is responsive to the substrate bias voltage detection signal outputted from the substrate bias voltage detector circuit, and outputs a drive signal when the absolute value of the substrate bias voltage is equal to or smaller than a predetermined value, and stops outputting the drive signal when the absolute value of the substrate bias voltage is larger than the predetermined value. The charge pump circuit is responsive to the drive signal from the substrate bias driver circuit, and generates the substrate bias voltage.
Inventors
- 👤 Keiji Maruyama
- 👤 Naokazu Miyawaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:51
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205; G11; G11C; G11C5/00; G11C5/14; G11C5/147; H; H10; H10D; H10D89/00; H10D89/211; H10D89/213; H10D89/215
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
166 words
A substrate bias voltage generator circuit comprising: a substrate bias voltage detector circuit for detecting a substrate bias voltage applied to a semiconductor substrate and for outputting a substrate bias voltage detection signal, said substrate bias voltage detector circuit comprising a P-channel transistor having a gate terminal connected to said semiconductor substrate and an N-channel transistor having a substrate terminal connected to said semiconductor substrate, said substrate bias voltage applying a back bias voltage to said N-channel transistor; a substrate bias driver circuit, responsive to said substrate bias voltage detection signal outputted from said substrate bias voltage detector circuit, for outputting a drive signal when an absolute value of said substrate bias voltage is equal to or smaller than a predetermined value, and for not outputting said drive signal when an absolute value of said substrate bias voltage is larger than said predetermined value; and a charge pump circuit, responsive to said drive signal from said substrate bias driver circuit, for generating said substrate bias voltage.
Claim 2
Dependent Claim
166 words
A substrate bias voltage generator circuit comprising: a substrate bias voltage detector circuit for detecting a substrate bias voltage applied to a semiconductor substrate and for outputting a substrate bias voltage detection signal, said substrate bias voltage detector circuit comprising a P-channel transistor having a gate terminal connected to said semiconductor substrate and an N-channel transistor having a substrate terminal connected to said semiconductor substrate, said substrate bias voltage applying a back bias voltage to said N-channel transistor; a substrate bias driver circuit, responsive to said substrate bias voltage detection signal outputted from said substrate bias voltage detector circuit, for outputting a drive signal when an absolute value of said substrate bias voltage is equal to or smaller than a predetermined value, and for not outputting said drive signal when an absolute value of said substrate bias voltage is larger than said predetermined value; and a charge pump circuit, responsive to said drive signal from said substrate bias driver circuit, for generating said substrate bias voltage.
Claim 3
Dependent Claim
118 words
A substrate bias voltage generator circuit according to claim 1, wherein said substrate bias voltage detector circuit further comprises: a load element having a first end terminal and a second end terminal and being connected at said first end terminal to a power supply voltage terminal, said load element being normally on; and a driver circuit connected at one end terminal to said second end terminal of said load element, and connected at another end terminal to a ground potential terminal, said driver circuit including said P-channel transistor, wherein said substrate bias voltage detection signal is generated at a node interconnecting said second end terminal of said load element and said another end terminal of said driver circuit.
Claim 4
Dependent Claim
55 words
A substrate bias voltage generator circuit according to claim 2, wherein said load element is a P-channel transistor having a source terminal connected to said power supply voltage terminal, a drain terminal connected to an end terminal of said P-channel transistor of said driver circuit, and a gate terminal connected to said ground potential terminal.
Claim 5
Dependent Claim
36 words
A substrate bias voltage generator circuit according to claim 2, wherein said load element is a resistor connected between said power supply voltage terminal and an end terminal of said P-channel transistor of said driver circuit.
Claim 6
Dependent Claim
18 words
A substrate bias voltage generator circuit according to claim 2 wherein said N-channel transistor is said load element.
Claim 7
Dependent Claim
25 words
A substrate bias voltage generator circuit according to claim 2 wherein said N-channel transistor is located in an inverter train driven by said P-channel transistor.
Claim 8
Dependent Claim
47 words
A substrate bias voltage generator circuit according to claim 2 wherein: said N-channel transistor is said load element; and said detector circuit further comprising a train of inverters each including an N-channel transistor having a substrate terminal connected to said substrate and to said substrate bias voltage.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1996-09-06 | 1997-03-08 | 1997-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-06 | 2001-03-08 | 2001-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-06 | 2005-03-08 | 2005-09-07 | $7700.00 | Window Closed / Lapsed |