US5239747A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming integrated circuit devices
Assignee: STMicroelectronics lnc USA
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Filing: 1991-09-18
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Granted: 1993-08-31
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Expires: 2011-09-18
Abstract
Abstract A plurality of integrated circuit devices are bonded to a substrate. Signal traces for corresponding pins of the devices are run to the same location, but are not electrically connected. They are, however, located in close physical proximity at a designated location. At this designated location, a properly shaped and sized contact can be used to contact all of the corresponding traces simultaneously, allowing parallel burn-in of all devices on the substrate to be performed. The devices can still be tested individually after burn-in. Once functionality of the overall subsystem has been confirmed and encapsulation completed, a permanent contact can be made at the designated location to all traces simultaneously so that the devices will be in parallel, and the substrate can be encapsulated to form a completed subsystem.
Inventors
- 👤 Charles R. Ewers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 10:05
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2855; G01R31/2856; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/1201; G11C29/48; H; H05; H05K; H05K1/00; H05K1/02; H05K1/0266; H05K1/0268; H05K1/11; H05K1/117; H10; H10P; H10P74/00; H10P74/23; G01R31/286; G01R31/2863; G11C29/18; G11C29/26; G11C2029/2602; H05K1/03; H05K1/0306; H05K2201/00; H05K2201/03; H05K2201/0332; H05K2201/0364; H05K2201/0373; H05K2201/09; H05K2201/09209; H05K2201/09654; H05K2201/09663; H05K2201/10; H05K2201/10007; H05K2201/10159; H05K2201/10613; H05K2201/10621; H05K2201/10689; H10P74/27; H10P74/273; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49144
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
166 words
A method of forming an electronic device, comprising the steps of: forming a plurality of conductive traces on an insulating substrate, wherein traces connected to corresponding locations on the substrate terminate in close physical proximity in designated regions of the substrate; attaching a plurality of integrated circuit devices to the substrate so that conductive leads thereof contact the conductive traces; contacting all of the traces in each designated region with a single contact which puts them electrically in parallel, and providing power and signals to the integrated circuit devices through the conductive traces to perform a burn-in of the integrated circuit devices; testing each integrated circuit device individually by contacting individually the traces at each designated region for each integrated circuit, wherein the contacts at each designated region are removed prior to such testing; and permanently attaching a conductive contact at each designated region to connect all of the conductive traces terminating in the designated regions in parallel and to provide a connector to the device.
Claim 2
Independent Claim
166 words
A method of forming an electronic device, comprising the steps of: forming a plurality of conductive traces on an insulating substrate, wherein traces connected to corresponding locations on the substrate terminate in close physical proximity in designated regions of the substrate; attaching a plurality of integrated circuit devices to the substrate so that conductive leads thereof contact the conductive traces; contacting all of the traces in each designated region with a single contact which puts them electrically in parallel, and providing power and signals to the integrated circuit devices through the conductive traces to perform a burn-in of the integrated circuit devices; testing each integrated circuit device individually by contacting individually the traces at each designated region for each integrated circuit, wherein the contacts at each designated region are removed prior to such testing; and permanently attaching a conductive contact at each designated region to connect all of the conductive traces terminating in the designated regions in parallel and to provide a connector to the device.
Claim 3
Dependent Claim
48 words
The method of claim 1, further comprising the steps of: after said testing step, removing any integrated circuit devices which fail such testing step; replacing any removed integrated circuit devices with new integrated circuit devices; and repeating said contacting and testing steps for the new integrated circuit devices.
Claim 4
Dependent Claim
22 words
The method of claim 1, further comprising the step of: encapsulating the substrate and the integrated circuit devices in a protective coating.
Claim 5
Dependent Claim
20 words
The method of claim 3, wherein said covering step is performed before said step of permanently attaching the conductive contacts.
References Cited (Backward Citations)
US3835530A
Cited
US3702025A
Cited
US3606679A
Cited
US3993934A
Cited
US4866508A
Cited
US4924589A
Cited
US5020219A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-30 | 1997-03-01 | 1997-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-30 | 2001-03-01 | 2001-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-30 | 2005-03-01 | 2005-08-31 | $7700.00 | Window Closed / Lapsed |