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US5239509A
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1992-01-23
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Granted: 1993-08-24
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Expires: 2012-01-23
Abstract
Abstract A semiconductor memory device having: a RAM port for randomly accessing a memory cell array having memory cells disposed in matrix; a SAM port for serially accessing data of one row of the memory cell array; a mode switching unit for switching the operation mode of the SAM port between an ordinary data output mode and a test mode, upon externally receiving a mode switching signal; and an address pointer outputting unit for outputting an address pointer of the SAM port when the operation mode is switched to the test mode by the mode switching unit.
Inventors
- 👤 Tatsuo Ikawa
- 👤 Shigeo Ohshima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:00
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/20; G11C29/02; G11C7/00; G11C7/10; G11C7/1075
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
94 words
A semiconductor memory device comprising: a RAM port for randomly accessing a memory cell array having memory cells disposed in matrix; a SAM port for serially accessing data of one row of said memory cell array; mode switching means for switching the operation mode of said SAM port between an ordinary data output mode and a test mode, upon externally receiving a mode switching signal; and address pointer outputting means for outputting an address pointer of said SAM port when the operation mode is switched to said test mode by said mode switching means.
Claim 2
Dependent Claim
94 words
A semiconductor memory device comprising: a RAM port for randomly accessing a memory cell array having memory cells disposed in matrix; a SAM port for serially accessing data of one row of said memory cell array; mode switching means for switching the operation mode of said SAM port between an ordinary data output mode and a test mode, upon externally receiving a mode switching signal; and address pointer outputting means for outputting an address pointer of said SAM port when the operation mode is switched to said test mode by said mode switching means.
Claim 3
Dependent Claim
33 words
A semiconductor memory device according to claim 1, wherein said address pointer outputting means includes an output buffer circuit which is the same output buffer circuit for outputting data from said SAM port.
Claim 4
Dependent Claim
66 words
A semiconductor memory device according to claim 2, further comprising means for dividing said address pointer into at least two parts and obtaining a logical sum of each part, and means for supplying said logical sum to said address pointer outputting means to output said address pointer, if the bit configuration of said SAM port is smaller than the number of bits of said address pointer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-23 | 1997-02-22 | 1997-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-23 | 2001-02-22 | 2001-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-23 | 2005-02-22 | 2005-08-24 | $7700.00 | Window Closed / Lapsed |