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US5236867A Expired / Lapsed US ⏱️ 0.0 years remaining

Manufacturing method of contact hole arrangement of a semiconductor device

Assignee: Panasonic Holdings Corp
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Filing: 1992-01-17
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Granted: 1993-08-17
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Expires: 2012-01-17
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Abstract

Abstract A semiconductor device includes first and second oxide film regions formed on a surface of a semiconductor substrate. A first impurity diffusion region is located at a distance from one of the first and second oxide regions. A second impurity diffusion region is located along the surface of the semiconductor substrate and partially overlaps the first impurity diffusion region. The width of the second impurity diffusion region is greater than that of the first impurity diffusion region. A contact hole is provided extending substantially over the second impurity diffusion region. The contact hole has a first side wall defined by one of the first and second oxide film regions and a second side wall defined by an insulating film. The width of the opening of the contact hole is greater than or equal to the width of the first impurity diffusion region. A conductive film is formed along the bottom portion and along the opposite side walls of the contact hole. A wiring layer is provided connected to the conductive film.

Inventors

  • 👤 Takashi Furuta
  • 👤 Shuichi Nishida

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 08:35
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 309 words
A method of manufacturing a semiconductor device comprising: a first step of forming first and second oxide film regions respectively at first and second locations on a surface of a semiconductor substrate of a first type of conductivity, said first and second oxide film regions defining a first direction therebetween; a second step of forming a first impurity diffusion region of a second type of conductivity extending a first distance in said first direction between said first and second oxide film regions along said surface of said semiconductor substrate and spaced from said second oxide film region and directly adjacent said first oxide film region; a third step of forming a first insulation film on said surface of said semiconductor substrate to cover at least said first oxide film region and said first impurity diffusion region; a fourth step of forming a contact hole, which extends a second distance in said first direction in said first insulation film, by removing a continuous portion of said insulation film which extends over a portion of said first impurity diffusion region and an adjacent edge portion of said first oxide film region, and by removing said adjacent edge portion of said first oxide film region; a fifth step of forming a conductive film on at least a bottom surface of said contact hole, said bottom surface extending said second distance in said first direction; a sixth step of forming a second impurity diffusion region, extending a third distance in said first direction along said surface of said semiconductor substrate and partially overlapping said first impurity diffusion region, by introducing impurities of the second type of conductivity into said semiconductor substrate through said conductive film, said third distance being greater than each of said first and second distances; and, a seventh step of forming a wiring layer in contact with said conductive layer.
Claim 2
Independent Claim 309 words
A method of manufacturing a semiconductor device comprising: a first step of forming first and second oxide film regions respectively at first and second locations on a surface of a semiconductor substrate of a first type of conductivity, said first and second oxide film regions defining a first direction therebetween; a second step of forming a first impurity diffusion region of a second type of conductivity extending a first distance in said first direction between said first and second oxide film regions along said surface of said semiconductor substrate and spaced from said second oxide film region and directly adjacent said first oxide film region; a third step of forming a first insulation film on said surface of said semiconductor substrate to cover at least said first oxide film region and said first impurity diffusion region; a fourth step of forming a contact hole, which extends a second distance in said first direction in said first insulation film, by removing a continuous portion of said insulation film which extends over a portion of said first impurity diffusion region and an adjacent edge portion of said first oxide film region, and by removing said adjacent edge portion of said first oxide film region; a fifth step of forming a conductive film on at least a bottom surface of said contact hole, said bottom surface extending said second distance in said first direction; a sixth step of forming a second impurity diffusion region, extending a third distance in said first direction along said surface of said semiconductor substrate and partially overlapping said first impurity diffusion region, by introducing impurities of the second type of conductivity into said semiconductor substrate through said conductive film, said third distance being greater than each of said first and second distances; and, a seventh step of forming a wiring layer in contact with said conductive layer.
Claim 3
Dependent Claim 113 words
A method as recited in claim 1, wherein said fifth step further includes forming said conductive film continuously on opposite inner side walls of said contact hole and on a portion of an upper surface of said first insulation film, and wherein said method further comprises, prior to said seventh step, the steps of: forming a second insulation film on said conductive film and said first insulation layer; and, forming a second contact hole, which extends a fourth distance in said first direction in said second insulation film, by removing a continuous portion of said second insulation film located over said first contact hole, said fourth distance being greater than said second distance.
Claim 4
Dependent Claim 16 words
A method as recited in claim 2, comprising using polysilicon or polycide as said conductive film.
Claim 5
Dependent Claim 16 words
A method as recited in claim 1, comprising using polysilicon or polycide as said conductive film.

References Cited (Backward Citations)

US3915767A Cited
US4477962A Cited
US4332839A Cited
GB2075255A Cited
US4433468A Cited
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US4512073A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-08-16 1997-02-15 1997-08-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-08-16 2001-02-15 2001-08-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-08-16 2005-02-15 2005-08-17 $7700.00 Window Closed / Lapsed

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