Semiconductor integrated circuit device

Claim 1

A semiconductor device comprising: a plurality of word lines; a plurality of data lines disposed over said word lines; a plurality of source lines; a plurality of memory cells, said plurality of word and data lines being arrayed as a combination of substantially perpendicularly directioned lines, wherein each combination of one of said plurality of word lines and one of said plurality of data lines defines a different one of said plurality of memory cells, wherein each of said plurality of memory cells comprises a single transistor including a control gate coupled to an associated one of said plurality of word lines, a floating gate positioned under said control gate, a source region coupled to an associated one of said plurality of source lines, and a drain region coupled to an associated one of said plurality of data lines, said source and drain regions being formed in a semiconductor substrate, and wherein said source lines are substantially buried in said device between said word lines and are formed substantially in self-alignment with said control and floating gates of each memory cell associated therewith; insulating films formed substantially in self-alignment with said control and floating gates of said each memory cell, said source lines being disposed in said device between said insulating films; and element isolating insulating films substantially buried in said device between said floating gates of said memory cells, wherein said source lines are respectively interposed between said element isolating insulating films in said device, wherein said element isolating insulating films are formed substantially in self-alignment with said floating gates of said memory cells, and wherein said element isolating insulating films and said floating gates have upper principal surfaces that are coplanar.