Method for operating data processors

Claim 2

In an information processing system including: a central processor (CP) and an arithmetic processor (AU), each responsive to a unit clock signal having a predetermined period, and each performing respective successive instruction execution cycles having periods which are multiples of the period of said unit clock signal; a method for synchronizing a start of an instruction execution cycle of said CP to a start of an instruction execution cycle of said AU, comprising steps of: in said CP: recognizing a request for synchronization of said CP to said AU; then completing a current instruction execution cycle; asserting a first signal when said current instruction execution cycle is complete; then suspending performance of any further instruction execution cycles; and resuming performance of succeeding instruction execution cycles at a next transition of said unit clock signal after a second signal is detected; in said AU: recognizing a request for synchronizing of said AU to said CP; then completing a current instruction execution cycle; asserting said second signal when said current instruction execution cycle is complete; then suspending performance of any further instruction execution cycles; and resuming performance of succeeding instruction execution cycles at a next transition of said unit clock signal after said first signal is detected.

Claim 3

A method as set forth in claim 1 where in the AU each instruction execution cycle comprises execution of a sequence of microinstructions, and the step of completing the current instruction execution cycle includes steps of: executing a final microinstruction; and asserting a third signal to indicate a not busy condition to the CP.

Claim 4

A method as set forth in claim 2 wherein if the CP determines that it is not prepared to begin a next succeeding instruction execution cycle, said CP further performs a step of asserting a fourth signal; and said AU performs a step of suspending succeeding instruction execution cycles when said fourth signal is detected.

Claim 5

In a data processing system having a memory means, a first data processing means, coupled to said memory means, and a second data processing means, coupled to said first data processing means and said memory means, a method of executing an instruction of a type which operates on a first operand located at a first address and having a first length in bytes in the memory means and a second operand located at a second address and having a second length in bytes within the memory means, to produce a result which is stored in the memory means, comprising steps of: decoding the instruction in the first data processing means to extract information relating to the instruction, including at least a portion of the first address, the first length in bytes, at least a portion of the second address and the second length in bytes; providing the first length, the second length and the portion of the first address to the second data processing means; determining, within the second data processing means, from the first length and the portion of the first address, a first number of memory means read cycles required to retrieve the first operand from said memory means; retrieving the first operand from said memory means by executing, under control of said first data processing means, the first number of memory means read cycles; providing at least a portion of the first operand and the portion of the second address to said second data processing means; determining within the second data processing means from the second length and the portion of the second address a second number of member means read cycles required to retrieve the second operand from said memory means; retrieving the second operand from said memory means by executing, under control of said first data processing means, the determined number of memory means read cycles required to read the second operand from said memory means, providing at least a portion of the second operand to the second data processing means; executing the instruction within the second data processing means to generate the result; determining within the second data processing means from the first length and the portion of the first address a number of memory means write cycles required to store the result in the memory means; and storing the result in the memory means at the first address by executing the number of memory means write cycles required to store the result.

Claim 6

In a data processing system having a memory means, a first data processing means, coupled to said memory means, and a second data processing means, coupled to said first data processing means and said memory means, a method of executing an instruction of a type which operates on a first operand located at a first address and having a first length in bytes in the memory means and a second operand located at a second address and having a second length in bytes within the memory means, to produce a result which is stored in the memory means, comprising steps of: decoding the instruction in the first data processing means to extract information relating to the instruction, including at least a portion of the first address, the first length in bytes, at least a portion of the second address and the second length in bytes; providing the first length, the second length and the portion of the first address to the second data processing means; determining, within the second data processing means, from the first length and the portion of the first address, a first number of memory means read cycles required to retrieve the first operand from said memory means; retrieving the first operand from said memory means by executing, under control of said first data processing means, the first number of memory means read cycles; providing at least a portion of the first operand and the portion of the second address to said second data processing means; determining within the second data processing means from the second length and the portion of the second address a second number of member means read cycles required to retrieve the second operand from said memory means; retrieving the second operand from said memory means by executing, under control of said first data processing means, the determined number of memory means read cycles required to read the second operand from said memory means, providing at least a portion of the second operand to the second data processing means; executing the instruction within the second data processing means to generate the result; determining within the second data processing means from the first length and the portion of the first address a number of memory means write cycles required to store the result in the memory means; and storing the result in the memory means at the first address by executing the number of memory means write cycles required to store the result.

Claim 7

A method as set forth in claim 4 wherein each of the steps of determining includes steps of: generating within the second data processing means a plurality of NWAY branch signals; and providing the plurality of NWAY branch signals to the first data processing means.

Claim 8

A method as set forth in claim 4 wherein the result has a length in bytes, and the step of determining a number of members means write cycles further includes steps of: comparing the length of the result to the length of the first operand and; if the result is determined to have a length which exceeds the length of the first operand, generating an exception signal.

Claim 9

A method as set forth in claim 4 wherein said first and second data processing means respectively execute successive microinstruction cycles in response to respective microinstruction clock signals each related to transitions of a reference clock signal, and each of the steps of providing includes a step of synchronizing the microinstruction clock signal of the first data processing means to the microinstruction clock signal of the second data processing means, the step of synchronizing including steps of: in said first data processing means: generating a request for synchronization; completing a currently executing microinstruction cycle; asserting a first signal which indicates that the currently executing microinstruction cycle is complete; then suspending execution of microinstruction cycles; and resuming execution of successive microinstruction cycles at a next transition of the reference clock signal when a second signal is detected; in said second data processing means: generating a request for synchronization; completing a currently executing microinstruction cycle; asserting said second signal which indicates that the currently executing microinstruction cycle is complete; then suspending execution of microinstruction cycles; and resuming execution of successive microinstruction cycles at a next transition of the reference clock signal when said first signal is detected.

Claim 10

A method as set forth in claim 4 wherein said first operand has a predetermined alignment within the memory means and wherein the step of executing includes, if necessary, a step of aligning the result within the second data processing means such that the alignment of the result within the memory means is the same as the alignment of the first operand within the memory means.

Claim 11

A method as set forth in claim 4 wherein said first operand has a first predetermined alignment within the memory means and said second operand has a second predetermined alignment within the memory means; and wherein: the step of providing at least a portion of the first operand includes, if necessary, a step of aligning the portion of the first operand; and the step of providing at least a portion of the second operand includes, if necessary, a step of aligning the portion of the second operand.