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Patent US5233566A successfully refreshed from Google Patents.
US5233566A
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Address detector of a redundancy memory cell
Assignee: Toshiba Corp
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Filing: 1990-11-16
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Granted: 1993-08-03
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Expires: 2010-11-16
Abstract
Abstract An address detector of a redundancy memory cell is provided including a programming element for storing address data for replacing a defective cell with the redundancy cell. In a test mode, the redundancy cell may be written to regardless of whether or not a memory cell is defective. Thus, the redundancy cell may be tested without programming a programming element that replaces a defective cell with a redundancy cell. The detector further includes a latch for latching the state of the programming element, and a data setting element for setting the latch in a test mode.
Inventors
- 👤 Keniti Imamiya
- 👤 Shigeru Atsumi
- 👤 Sumio Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 23:08
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/785; G11C29/789; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/24
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
65 words
An addressing circuit for use with a memory cell of a semiconductor memory device, comprising: a redundancy memory cell; a fuse for replacing the memory cell with said redundancy cell, said fuse having at least two possible states; a latch means for latching the state of said fuse; and a data setting means for setting said latch means regardless of the state of said fuse.
Claim 2
Dependent Claim
65 words
An addressing circuit for use with a memory cell of a semiconductor memory device, comprising: a redundancy memory cell; a fuse for replacing the memory cell with said redundancy cell, said fuse having at least two possible states; a latch means for latching the state of said fuse; and a data setting means for setting said latch means regardless of the state of said fuse.
Claim 3
Dependent Claim
81 words
An addressing circuit for use with a semiconductor memory device having a memory cell and a redundancy said memory cell in the event that it is defective, said circuit comprising: a programming element having at least two possible states for respectively enabling and disabling the addressing of said redundancy cell; a latch means for latching the state of said programming element; and a data setting means for, in a test mode, setting said latch means to either of said two states.
Claim 4
Dependent Claim
81 words
An addressing circuit for use with a semiconductor memory device having a memory cell and a redundancy said memory cell in the event that it is defective, said circuit comprising: a programming element having at least two possible states for respectively enabling and disabling the addressing of said redundancy cell; a latch means for latching the state of said programming element; and a data setting means for, in a test mode, setting said latch means to either of said two states.
Claim 5
Dependent Claim
14 words
The addressing circuit according to claim 2, wherein said programming element comprises a fuse.
Claim 6
Dependent Claim
16 words
The addressing circuit according to claim 2, wherein said data setting means comprises a FAMOS transistor.
Claim 7
Dependent Claim
53 words
The addressing circuit according to claim 4, further comprising: a write control circuit for supplying a write signal to said data setting means; and a transistor having its drain coupled to a drain of said FAMOS transistor, its source coupled to a power supply, and its gate coupled to said write control circuit.
Claim 8
Dependent Claim
28 words
The addressing circuit according to claim 2, further comprising: a bonding pad coupled to said data setting means for supplying a write signal to said data setting means.
Claim 9
Dependent Claim
30 words
The addressing according to claim 2, further comprising a switch means for selectively coupling said latch means to said programming element and said latch means to said data setting means.
Claim 10
Dependent Claim
22 words
The addressing circuit according to claim 7, further comprising a bonding pad for receiving a control signal for controlling said switch means.
Claim 11
Dependent Claim
103 words
A semiconductor memory device comprising: a memory cell array having a plurality of word lines and bit lines; a redundancy cell array coupled to said bit lines of said memory cell array and for respectively replacing memory cells of said memory cell array in the event they are defective; a programming element having two states for respectively enabling and disabling the addressing of one of said redundancy cells; a latch means for latching the state of said programming element; and a data setting means for, in a test mode, setting said latch means to enable or disable the addressing of said redundancy cell.
Claim 12
Dependent Claim
103 words
A semiconductor memory device comprising: a memory cell array having a plurality of word lines and bit lines; a redundancy cell array coupled to said bit lines of said memory cell array and for respectively replacing memory cells of said memory cell array in the event they are defective; a programming element having two states for respectively enabling and disabling the addressing of one of said redundancy cells; a latch means for latching the state of said programming element; and a data setting means for, in a test mode, setting said latch means to enable or disable the addressing of said redundancy cell.
Claim 13
Dependent Claim
71 words
The semiconductor memory device according to claim 9, further comprising: a memory cell address decoder for decoding an address signal of said memory cell array; a redundancy cell address decoder for detecting when a defective address of said memory cell array has been selected by said address signal; and a redundancy decoder for selecting an address of said redundancy cell array to replace said defective address of said memory cell array.
Claim 14
Dependent Claim
15 words
The semiconductor memory device according to claim 9, wherein said programming element comprises a fuse.
Claim 15
Dependent Claim
17 words
The semiconductor memory device according to claim 9, wherein said data setting means comprises a FAMOS transistor.
Claim 16
Dependent Claim
54 words
The semiconductor memory device according to claim 12, further comprising: a write control circuit for supplying a write signal to said data setting means; and a transistor having its drain coupled to a drain of said FAMOS transistor, its source coupled to a power supply, and its gate coupled to said write control circuit.
Claim 17
Dependent Claim
29 words
The semiconductor memory device according to claim 9, further comprising: a bonding pad coupled to said data setting means for supplying a wrtie signal to said data setting means.
Claim 18
Dependent Claim
32 words
The semiconductor memory device according to claim 9, further comprising a switch means for selectively coupling said latch means to said programming element and said latch means to said data setting means.
Claim 19
Dependent Claim
23 words
The semiconductor memory device according to claim 15, further comprising a bonding pad for receiving a control signal for controlling said switch means.
Claim 20
Dependent Claim
110 words
A semiconductor memory device comprising: a memory cell array having a plurality of word lines and bit lines; a redundancy cell array, coupled to said bit lines of said memory cell array, for respectively replacing memory cells of said memory cell array in the event that they are defective; a first means for specifying address information representing which cell of the memory cell array is to be replaced by a cell of the redundancy cell array; and a second means for specifying, for a predetermined period of time, address information representing which cell of the memory cell array is to be replaced by a cell of the redundancy cell array.
Claim 21
Dependent Claim
110 words
A semiconductor memory device comprising: a memory cell array having a plurality of word lines and bit lines; a redundancy cell array, coupled to said bit lines of said memory cell array, for respectively replacing memory cells of said memory cell array in the event that they are defective; a first means for specifying address information representing which cell of the memory cell array is to be replaced by a cell of the redundancy cell array; and a second means for specifying, for a predetermined period of time, address information representing which cell of the memory cell array is to be replaced by a cell of the redundancy cell array.
Claim 22
Dependent Claim
15 words
The semiconductor memory device according to claim 17, wherein said first means comprises a fuse.
Claim 23
Dependent Claim
16 words
The semiconductor memory device according to claim 17, wherein said second means comprises a FAMOS transistor.
Claim 24
Dependent Claim
53 words
The semiconductor memory device according to claim 19, further comprising: a write control circuit for supplying a write signal to said FAMOS transistors; and a transistor having its drain coupled to a drain of said FAMOS transistor, its source coupled to a power supply, and its gate coupled to said write control circuit.
Claim 25
Dependent Claim
27 words
The semiconductor memory device according to claim 17, further comprising: a bonding pad coupled to said second means for supplying a write signal to said second means.
Claim 26
Dependent Claim
21 words
The semiconductor memory device according to claim 17, further comprising a latch means for latching the state of said first means.
Claim 27
Dependent Claim
31 words
The semiconductor memory device according to claim 22, further comprising a switch means for selectively coupling said latch means to said first means and said latch means to said second means.
Claim 28
Dependent Claim
23 words
The semiconductor memory device according to claim 23, further comprising a bonding pad for receiving a control signal for controlling said switch means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-02 | 1997-02-01 | 1997-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-02 | 2001-02-01 | 2001-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-02 | 2005-02-01 | 2005-08-03 | $7700.00 | Window Closed / Lapsed |