Glitch trigger circuit

Claim 2

A glitch trigger circuit (6A) comprising: (a) a timer circuit (10) including means (20) for generating a ramp signal upon the command of an input signal, means (50) for generating an end of ramp signal when the ramp signal reaches a predetermined magnitude, wherein the difference in time between the end of ramp signal and the input signal defines a first time interval, means (80) for counting initiated by the end of ramp signal and producing a terminal count signal when a predetermined number of clock cycles have been counted, wherein the predetermined number of cycles defines a second time interval, and means (100) for providing an output signal that is responsive to the end of ramp signal and the terminal count signal and is accordingly delayed from the input signal by a total time interval substantially equal to the sum of the first and second time intervals; and (b) a flip-flop (113)having a first inverted input for receiving the input signal, a second inverted input for receiving the output signal, and an output for providing a trigger signal upon detection of an input signal having a pulse width less than a predetermined time interval.

Claim 3

A glitch trigger circuit (6A) as in claim 1 further comprising means (111) for delaying the input signal to the first inverted input of the flip-flop by an amount not greater than a characteristic reset time of the timer circuit.

Claim 4

A glitch trigger circuit (6A) as in claim 1 in which the flip-flop includes a reset input, and the glitch trigger circuit further comprises means (115) for coupling a delayed trigger signal to the reset input.

Claim 5

A glitch filter circuit (6B) comprising: (a) a timer circuit (10) including means (20) for generating a ramp signal upon the command of an input signal, means (50) for generating an end of ramp signal when the ramp signal reaches a predetermined magnitude, wherein the difference in time between the end of ramp signal and the input signal defines a first time interval, means (80) for counting initiated by the end of ramp signal and producing a terminal count signal when a predetermined number of clock cycles have been counted, wherein the predetermined number of cycles defines a second time interval, and means (100) for providing an output signal that is responsive to the end of ramp signal and the terminal count signal and is accordingly delayed from the input signal by a total time interval substantially equal to the sum of the first and second time intervals; and (b) a flip-flop (113) having a first inverted input for receiving the input signal, a second non-inverted input for receiving the output signal, and an output for providing a trigger signal upon detection of an input signal having a pulse width greater than a predetermined time interval.

Claim 6

A glitch filter circuit (6B) comprising: (a) a timer circuit (10) including means (20) for generating a ramp signal upon the command of an input signal, means (50) for generating an end of ramp signal when the ramp signal reaches a predetermined magnitude, wherein the difference in time between the end of ramp signal and the input signal defines a first time interval, means (80) for counting initiated by the end of ramp signal and producing a terminal count signal when a predetermined number of clock cycles have been counted, wherein the predetermined number of cycles defines a second time interval, and means (100) for providing an output signal that is responsive to the end of ramp signal and the terminal count signal and is accordingly delayed from the input signal by a total time interval substantially equal to the sum of the first and second time intervals; and (b) a flip-flop (113) having a first inverted input for receiving the input signal, a second non-inverted input for receiving the output signal, and an output for providing a trigger signal upon detection of an input signal having a pulse width greater than a predetermined time interval.

Claim 7

A glitch filter circuit (6B) as in claim 4 further comprising means (111) for delaying the input signal to the first inverted input of the flip-flop by an amount not greater than a characteristic reset time of the timer circuit.

Claim 8

A glitch filter circuit (6B) as in claim 4 in which the flip-flop includes a reset input, and the glitch filter circuit further comprises means (115) for coupling a delayed trigger signal to the reset input.

Claim 9

A trigger circuit (6C, 6D, 6E, 6F) comprising: (a) first and second timer circuit (10A, 10B), each timer circuit including means (20) for generating a ramp signal upon the command of an input signal, means (50) for generating an end of ramp signal when the ramp signal reaches a predetermined magnitude, wherein the difference in time between the end of ramp signal and the input signal defines a first time interval, means (80) for counting initiated by the end of ramp signal and producing a terminal count signal when a predetermined number of cycles defines a second time interval, and means (100) for providing an output signal that is responsive to the end of ramp signal and the input signal by a total time interval substantially equal to the sum of the first and second time intervals; (b) a first flip-flop (113) having a first input for receiving the input signal, a second input for receiving the output signal of the first timer circuit, and an output; (c) a second flip-flop (213) having a first input for receiving the input signal, a second input for receiving the output signal of the second timer circuit, and an output; and (d) logic means (117, 119) having first and second inputs respectively coupled to the outputs of the first and second flip-flops and an output for providing a trigger signal.

Claim 10

A trigger circuit (6C, 6D, 6E, 6F) comprising: (a) first and second timer circuit (10A, 10B), each timer circuit including means (20) for generating a ramp signal upon the command of an input signal, means (50) for generating an end of ramp signal when the ramp signal reaches a predetermined magnitude, wherein the difference in time between the end of ramp signal and the input signal defines a first time interval, means (80) for counting initiated by the end of ramp signal and producing a terminal count signal when a predetermined number of cycles defines a second time interval, and means (100) for providing an output signal that is responsive to the end of ramp signal and the input signal by a total time interval substantially equal to the sum of the first and second time intervals; (b) a first flip-flop (113) having a first input for receiving the input signal, a second input for receiving the output signal of the first timer circuit, and an output; (c) a second flip-flop (213) having a first input for receiving the input signal, a second input for receiving the output signal of the second timer circuit, and an output; and (d) logic means (117, 119) having first and second inputs respectively coupled to the outputs of the first and second flip-flops and an output for providing a trigger signal.

Claim 11

A trigger (6C) as in claim 7 in which the first timer circuit (10A) comprises a slow timer circuit programmed for a relatively longer time interval, the second timer circuit (10B) comprises a fast timer circuit programmed for a relatively shorter time interval, the first and second inputs of the first flip-flop (113) each comprise inverted inputs, the first input of the second flip-flop (213) comprises an inverted input, and the logic means (117) comprises an AND gate for providing a trigger signal upon detection of an input signal having a pulse width greater than the relatively shorter time interval determined by the second, fast timer circuit and less than the relatively longer time interval determined by the first, slow timer circuit.

Claim 12

A trigger circuit (6C) as in claim 8 further comprising: first means (111) for delaying the input signal to the first inverted input of the first flip-flop by an amount not greater than a characteristic reset time of the first timer circuit; and second means (211) for delaying the input signal to the first inverted input of the second flip-flop by an amount not greater than a characteristic reset time of the second timer circuit.

Claim 13

A trigger circuit (6C) as in claim 8 in which the first and second flip-flops each include a reset input, and the trigger circuit further comprises means (115) for coupling a delayed trigger signal to the reset inputs.

Claim 14

A trigger (6D) as in claim 7 in which the first timer circuit (10A) comprises a slow timer circuit programmed for a relatively longer time interval, the second timer circuit (10B) comprises a fast timer circuit programmed for a relatively shorter time interval, the first input of the first flip-flop (113) each comprises an inverted input, the first and second input of the second flip-flop (213) comprises an inverted input, and the logic means (119) comprises an OR gate for providing a trigger signal upon detection of an input signal having a pulse width less than the relatively shorter time interval determined by the second, fast timer circuit or greater than the relatively longer time interval determined by the first, slow timer circuit.

Claim 15

A trigger circuit (6D) as in claim 11 further comprising: first means (111) for delaying the input signal to the first inverted input of the first flip-flop by an amount not greater than a characteristic reset time of the first timer circuit; and second means (211) for delaying the input signal to the first inverted input of the second flip-flop by an amount not greater than a characteristic reset time of the second timer circuit.

Claim 16

A trigger circuit (6D) as in claim 11 in which the first and second flip-flops each include a reset input, and the trigger circuit further comprises means (115) for coupling a delayed trigger signal to the reset inputs.

Claim 17

A trigger circuit (6E) as in claim 7 in which the input of the second timer circuit (10B) comprises an inverted input, the first and second inputs of the first flip-flop (113) each comprise an inverted input, the first and second inputs of the second flip-flop (213) each comprise an inverted input, and the logic means (119) comprises an OR gate for providing a trigger signal upon detection of an input signal of a first polarity having a pulse width less than a time interval determined by the first timer circuit or an input signal of a second polarity having a pulse width less than a time interval determined by the second timer circuit.

Claim 18

A trigger circuit (6E) as in claim 14 further comprising: first means (111) for delaying the input signal to the first inverted input of the first flip-flop by an amount not greater than a characteristic reset time of the first timer circuit; and second means (211) for inverting and delaying the input signal to the first inverted input of the second flip-flop by an amount not greater than a characteristic reset time of the second timer circuit.

Claim 19

A trigger circuit (6E) as in claim 14 in which the first and second flip-flops each include a reset input, and the trigger circuit further comprises means (115) for coupling a delayed trigger signal to the reset inputs.

Claim 20

A trigger circuit (6F) as in claim 7 in which the input of the second timer circuit (10B) comprises an inverted input, the first input of the first flip-flop (113) comprises an inverted input, the first input of the second flip-flop (213) comprises an inverted input, and the logic means (119) comprises an OR gate for providing a trigger signal upon detection of an input signal of a first polarity having a pulse width greater than a time interval determined by the first timer circuit or an input signal of a second polarity having a pulse width greater than a time interval determined by the second timer circuit.

Claim 21

A trigger circuit (6F) as in claim 17 further comprising: first means (111) for delaying the input signal to the first inverted input of the first flip-flop by an amount not greater than a characteristic reset time of the first timer circuit; and second means (211) for inverting and delaying the input signal to the first inverted input of the second flip-flop by an amount not greater than a characteristic reset time of the second timer circuit.

Claim 22

A trigger circuit (6F) as in claim 17 in which the first and second flip-flops each include a reset input, and the trigger circuit further comprises means (115) for coupling a delayed trigger signal to the reset.