Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence

Claim 2

A cache memory system comprising: a cache memory having a plurality of memory lines for storing both branch target cache entries and at least one pre-fetch instruction queue; first means, operatively connected to said cache memory, for designating a majority of said lines as branch target entries containing branch target instruction words; second means, operatively connected to said cache memory, for designating a minority of said lines as pre-fetch instruction queues; control means, operatively connected to said first and second means, for dynamically altering, in accordance with an instruction sequence, the designations as either branch target entries or pre-fetch instruction queues of said cache memory lines, such that a single cache memory line can alternately be a pre-fetch instruction queue and a branch target entry; an instruction buffer coupled to said cache; wherein said control means including means for transferring instructions from a cache memory line currently designated as a pre-fetch instruction queue to said instruction buffer without requiring an intermediate transfer to a separate pre-fetch instruction queue location.

Claim 3

The cache memory of claim 1 further comprising valid bits for indicating the validity of said lines containing valid branch target entries and means for invalidating said valid bits for lines designated as pre-fetch instruction queues.

Claim 4

The cache memory of claim 1 further comprising: means for fetching initial instruction words into one of said pre-fetch instruction queues upon a branch to an instruction not in said cache memory; and control means for determining if said initial instruction words in said pre-fetch instruction queue should be designated as a branch target entry, and for preventing further fetches into said pre-fetch instruction queue until said determining is completed.

Claim 5

A cache memory comprising: a plurality of memory lines for storing both branch target cache entries and at least one pre-fetch instruction queue; first means, operatively connected to said cache memory, for designating a majority of said lines as branch target entries containing branch target instruction words; second means, operatively connected to said cache memory, for designating a minority of said lines as pre-fetch instruction queues; means, operatively connected to said first and second means, for dynamically altering, in accordance with an instruction sequence, the designations as either branch target entries or pre-fetch instruction queues of said cache memory lines, such that a single cache memory line can alternately be a pre-fetch instruction queue and a branch target entry; means for predicting the direction of a branch instruction; means for detecting a mispredicted branch direction; means for aborting partial instruction decoding when a mispredicted branch direction is detected; and means for reading from a main memory both a branch target entry and an initial pre-fetch instruction queue for an other than predicted direction of a branch while the actual direction of said branch is being determined.

Claim 6

A cache memory comprising: a plurality of memory lines for storing both branch target cache entries and at least one pre-fetch instruction queue; first means, operatively connected to said cache memory, for designating a majority of said lines as branch target entries containing branch target instruction words; second means, operatively connected to said cache memory, for designating a minority of said lines as pre-fetch instruction queues; means, operatively connected to said first and second means, for dynamically altering, in accordance with an instruction sequence, the designations as either branch target entries or pre-fetch instruction queues of said cache memory lines, such that a single cache memory line can alternately be a pre-fetch instruction queue and a branch target entry; means for predicting the direction of a branch instruction; means for detecting a mispredicted branch direction; means for aborting partial instruction decoding when a mispredicted branch direction is detected; and means for reading from a main memory both a branch target entry and an initial pre-fetch instruction queue for an other than predicted direction of a branch while the actual direction of said branch is being determined.

Claim 7

A cache memory comprising: a plurality of memory lines for storing both branch target cache entries and at least one pre-fetch instruction queue; first means operatively connected to said cache memory for designating a majority of said lines as branch target entries containing branch target instruction words; second means operatively connected to said cache memory for designating a minority of said lines as pre-fetch instruction queues; means operatively connected to said first and second means for dynamically altering, in accordance with an instruction sequence, the designations as either branch target entries or pre-fetch instruction queues of said cache memory lines, such that a single cache memory line can alternately be a pre-fetch instruction queue and a branch target entry; valid bits for indicating the validity of said lines containing valid branch target entries and means for invalidating said valid bits for lines designated as pre-fetch instruction queues; means for fetching initial instruction words into one of said pre-fetch instruction queues upon a branch to an instruction not in said cache memory; control means for determining if said initial instruction words in said pre-fetch instruction queue should be designated as a branch target entry, and for preventing further fetches into said pre-fetch instruction queue until said determining is completed; means for predicting the direction of a branch instruction; means for detecting a mispredicted branch direction; means for aborting partial instruction decoding when a mispredicted branch direction is detected; and means for reading from a main memory both a branch target entry and an initial pre-fetch instruction queue for an other than predicted direction of a branch while the actual direction of said branch is being determined.

Claim 8

A cache memory comprising: a plurality of memory lines for storing both branch target cache entries and at least one pre-fetch instruction queue; first means operatively connected to said cache memory for designating a majority of said lines as branch target entries containing branch target instruction words; second means operatively connected to said cache memory for designating a minority of said lines as pre-fetch instruction queues; means operatively connected to said first and second means for dynamically altering, in accordance with an instruction sequence, the designations as either branch target entries or pre-fetch instruction queues of said cache memory lines, such that a single cache memory line can alternately be a pre-fetch instruction queue and a branch target entry; valid bits for indicating the validity of said lines containing valid branch target entries and means for invalidating said valid bits for lines designated as pre-fetch instruction queues; means for fetching initial instruction words into one of said pre-fetch instruction queues upon a branch to an instruction not in said cache memory; control means for determining if said initial instruction words in said pre-fetch instruction queue should be designated as a branch target entry, and for preventing further fetches into said pre-fetch instruction queue until said determining is completed; means for predicting the direction of a branch instruction; means for detecting a mispredicted branch direction; means for aborting partial instruction decoding when a mispredicted branch direction is detected; and means for reading from a main memory both a branch target entry and an initial pre-fetch instruction queue for an other than predicted direction of a branch while the actual direction of said branch is being determined.