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Patent US5229966A successfully refreshed from Google Patents.
US5229966A
Expired / Lapsed
US
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Current control circuit for dynamic memory
Assignee: Toshiba Corp
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Filing: 1991-05-17
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Granted: 1993-07-20
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Expires: 2011-05-17
Abstract
Abstract As latch circuit is supplied with a readout control signal for reading out data and a reference voltage for determining "1" or "0" of address data. The latch circuit latches address data for selecting a memory cell array according to the readout control signal and the reference voltage. A reference voltage generation circuit for generating the reference voltage includes resistors connected between first and second power sources and an output node which is connected between the resistors and from which the reference voltage is output. A transistor serving as an interruption circuit for interrupting the current path is connected between the first power source and the resistor. The transistor is turned off to interrupt a through current flowing between the first and second power sources when the readout signal is set in the stand-by state.
Inventors
- 👤 Takashi Ohsawa
- 👤 Noriaki Ohba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:08
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074; G11C11/4076; G11C11/409; G11C11/4099
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
120 words
A current control circuit for a dynamic memory comprising: a memory cell array for storing data; a latch circuit for latching address data for selecting said memory cell array according to a readout control signal for reading out data and a reference voltage for determining "1" or "0" of the address data, the readout control signal having a readout state for reading out data and a stand-by state in which no data is read out; a reference voltage generation circuit having a resistor connected between first and second power sources, for generating the reference voltage; and an interruption circuit connected between said first power source and said resistor, for interrupting the current path between said first and second power sources.
Claim 2
Dependent Claim
120 words
A current control circuit for a dynamic memory comprising: a memory cell array for storing data; a latch circuit for latching address data for selecting said memory cell array according to a readout control signal for reading out data and a reference voltage for determining "1" or "0" of the address data, the readout control signal having a readout state for reading out data and a stand-by state in which no data is read out; a reference voltage generation circuit having a resistor connected between first and second power sources, for generating the reference voltage; and an interruption circuit connected between said first power source and said resistor, for interrupting the current path between said first and second power sources.
Claim 3
Dependent Claim
93 words
A circuit according to claim 1, wherein said reference voltage generation circuit includes first and second resistors connected between said first and second power sources and an output node connected between said first and second resistors to output the reference voltage, and said interruption circuit includes a first transistor connected between said output node and said first resistor and a second transistor connected between said output node and said second resistor, said first and second transistors being set in the off state when said readout control signal is set in the stand-by state.
Claim 4
Dependent Claim
17 words
A circuit according to claim 2, wherein said readout control signal is a /RAS (row address strobe).
Claim 5
Dependent Claim
153 words
A current control circuit for a dynamic memory comprising: a memory cell array for storing data; a latch circuit for latching address data for selecting said memory cell array according to a readout control signal for reading out data and a reference voltage for determining "1" or "0" of the address data, the readout control signal having a readout state for reading out data and a stand-by state in which no data is read out; a reference voltage generation circuit having a resistor connected between first and second power sources, for generating the reference voltage; an interruption circuit connected between said first power source and said resistor, for interrupting the current path between said first and second power sources; and a delay circuit for delaying supply of the readout address to said latch circuit until the reference voltage reaches a preset level when the readout control signal is set into the readout state.
Claim 6
Dependent Claim
153 words
A current control circuit for a dynamic memory comprising: a memory cell array for storing data; a latch circuit for latching address data for selecting said memory cell array according to a readout control signal for reading out data and a reference voltage for determining "1" or "0" of the address data, the readout control signal having a readout state for reading out data and a stand-by state in which no data is read out; a reference voltage generation circuit having a resistor connected between first and second power sources, for generating the reference voltage; an interruption circuit connected between said first power source and said resistor, for interrupting the current path between said first and second power sources; and a delay circuit for delaying supply of the readout address to said latch circuit until the reference voltage reaches a preset level when the readout control signal is set into the readout state.
Claim 7
Dependent Claim
93 words
A circuit according to claim 4, wherein said reference voltage generation circuit includes first and second resistors connected between said first and second power sources and an output node connected between said first and second resistors to output the reference voltage, and said interruption circuit includes a first transistor connected between said output node and said first resistor and a second transistor connected between said output node and said second resistor, said first and second transistors being set in the off state when said readout control signal is set in the stand-by state.
Claim 8
Dependent Claim
81 words
A circuit according to claim 4, wherein said delay circuit includes a delay circuit for delaying the readout control signal by a preset period of time; an OR circuit having one input terminal supplied with the readout control signal and the other input terminal supplied with an output signal of said delay circuit; and a signal generation circuit for generating a timing signal for controlling the latching timing of said latch circuit according to an output signal of said OR circuit.
Claim 9
Dependent Claim
75 words
A circuit according to claim 6, wherein said interruption circuit includes a delay circuit for delaying the readout control signal by a preset period of time; and an AND circuit having one input terminal supplied with the readout control signal and the other input terminal supplied with an output signal of said delay circuit, for detecting that the readout control signal is set at the high level for more than a preset period of time.
Claim 10
Dependent Claim
17 words
A circuit according to claim 7, wherein said readout control signal is a /RAS (row address strobe).
Claim 11
Dependent Claim
122 words
A current control circuit for a dynamic memory comprising: a memory cell array for storing data; a peripheral circuit for reading out data from said memory cell array according to a readout control signal, the readout control signal having a readout state for reading out data and a stand-by state in which no data is read out; a power source conversion circuit for converting a power source voltage to a preset potential and supplying the same to said peripheral circuit; and an interruption circuit connected between said power source conversion circuit and said peripheral circuit, for interrupting supply of the potential from said power source conversion circuit to said peripheral circuit when said readout control signal is set in the stand-by state.
Claim 12
Dependent Claim
122 words
A current control circuit for a dynamic memory comprising: a memory cell array for storing data; a peripheral circuit for reading out data from said memory cell array according to a readout control signal, the readout control signal having a readout state for reading out data and a stand-by state in which no data is read out; a power source conversion circuit for converting a power source voltage to a preset potential and supplying the same to said peripheral circuit; and an interruption circuit connected between said power source conversion circuit and said peripheral circuit, for interrupting supply of the potential from said power source conversion circuit to said peripheral circuit when said readout control signal is set in the stand-by state.
Claim 13
Dependent Claim
53 words
A circuit according to claim 9, wherein said readout control signal is a /RAS (row address strobe) and said interruption circuit includes a transistor which is connected between said power source conversion circuit and said peripheral circuit and is set into the off state when the /RAS is set at the high level.
Claim 14
Dependent Claim
68 words
A current control circuit for a dynamic memory comprising: a memory cell for storing data; a bit line for selecting said memory cell; a potential source for supplying a potential to said bit line; and a interruption circuit connected between said bit line and said potential source, for interrupting supply of a potential to said bit line when the readout control signal is set in the stand-by state.
Claim 15
Dependent Claim
68 words
A current control circuit for a dynamic memory comprising: a memory cell for storing data; a bit line for selecting said memory cell; a potential source for supplying a potential to said bit line; and a interruption circuit connected between said bit line and said potential source, for interrupting supply of a potential to said bit line when the readout control signal is set in the stand-by state.
Claim 16
Dependent Claim
105 words
A current control circuit for a dynamic memory comprising: a memory cell for storing data; a bit line for selecting said memory cell; a potential source for supplying a potential to said bit line; an interruption circuit connected between said bit line and said potential source, for interrupting supply of a potential to said bit line when the readout control signal is set in the stand-by state; and a supply circuit connected between said bit line and a preset potential Vss, for supplying a potential substantially equal to the potential to said bit line when the readout control signal is set in the stand-by state.
Claim 17
Dependent Claim
105 words
A current control circuit for a dynamic memory comprising: a memory cell for storing data; a bit line for selecting said memory cell; a potential source for supplying a potential to said bit line; an interruption circuit connected between said bit line and said potential source, for interrupting supply of a potential to said bit line when the readout control signal is set in the stand-by state; and a supply circuit connected between said bit line and a preset potential Vss, for supplying a potential substantially equal to the potential to said bit line when the readout control signal is set in the stand-by state.
Claim 18
Dependent Claim
63 words
A circuit according to claim 12, wherein said supply circuit includes a transistor which has a current path connected at one end to said bit line and is set in the ON state when the readout control signal is set in the stand-by state and a resistor connected between the other end of the current path of said transistor and said preset potential.
Claim 19
Dependent Claim
40 words
A circuit according to claim 12, wherein said readout control signal is a /RAS (row address strobe) and said interruption circuit includes a transistor which is set in the OFF state when the /RAS is set in the high level.
References Cited (Backward Citations)
US4937789A
Cited
US5001668A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-19 | 1997-01-18 | 1997-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-19 | 2001-01-18 | 2001-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-19 | 2005-01-18 | 2005-07-20 | $7700.00 | Window Closed / Lapsed |