Cmos digital-controlled delay gate

Claim 1

A CMOS digital-controlled delay gate comprising: an inverter circuit section formed of a plurality of parallel-connected inverters (12a-12n) having their inputs connected to an input node for receiving an input logic signal and their outputs connected to an output node for generating an output logic signal, each of said plurality of inverters being formed of a P-channel transistor (p1-pl) and an N-channel transistor (nl-nm), each of said P-channel transistors and N-channel transistors having predetermined sizes; a plurality of upper gating transistors (ps1-psl) having their conduction paths connected between a power supply potential (VCC) and a respective source electrode of said P-channel transistors of said plurality of inverters, each of said plurality of upper gating transistors having its gate connected to receive a corresponding one of first digital select signals (Sp1-Spl); a plurality of lower gating transistors (ns1-nsm) having their conduction paths connected between a ground potential and a respective source electrode of said N-channel transistors of said plurality of inverters, each of said plurality of lower gating transistors having its gate connected to receive a corresponding one of second digital select signals (sn1-snm); said first and second digital select signals having respective first and second numbers of different codes for selectively and independently turning on certain ones of said upper and lower gating transistors so as to enable at least one of the P-channel transistors and at least one of the N-channel transistors; and said inverter circuit section having a variable threshold voltage which is substantially determined by the ratio of the total P-channel transistor size to the total N-channel transistor size of said enabled transistors so that said output logic signal has a controllable propagation delay relative to said input logic signal.