Semiconductor integrated circuit device

Claim 2

A semiconductor integrated circuit device having its logical operation timing controlled by a clock synchronization and having a memory means in which input data is latched statically, said memory means comprising: a data input terminal to which said input data is inputted; a data output terminal from which output data is outputted from said memory means; a memory circuit, in which said input data is written and latched statically, coupled between said data input terminal and said data output terminal and having gate stages coupled between said data input terminal and data output terminal in series; a bypass circuit coupled in parallel to said memory circuit and having a smaller number of gate stages coupled in series between said data input terminal and said data output terminal than said memory circuit; and, switch means for conducting said input data through the bypass circuit to said data output terminal when said memory circuit is in a write state, and for conducting said input data through said memory circuit to said data output terminal when said memory circuit is in a latch state, said switch means being controlled by a clock signal supplied from outside said memory means, wherein said bypass circuit has a high level setting means for setting a high level to said data output terminal and a low level setting means for setting a low level to said data output terminal, and wherein said high level setting means and said low level setting means are selectively activated according to a level of said input data.

Claim 3

The semiconductor integrated circuit device according to claim 1, wherein said memory circuit has a write control switch for selectively inputting said input data to said memory circuit or not, wherein said write control switch is controlled by said clock signal.

Claim 4

The semiconductor integrated circuit device according to claim 1, wherein said memory circuit includes a driver circuit for driving a load to be coupled to said output terminal, wherein a drive ability of said high level setting means and said low level setting means are substantially equal to or larger than that of said driver circuit.

Claim 5

The semiconductor integrated circuit device according to claim 2, wherein said data output terminal includes a non-inversion data output terminal and an inversion data output terminal, wherein said memory means is coupled to both said non-inversion data output terminal and said inversion data output terminal and outputs a non-inversion output data which is not inverted as to said input data to said non-inversion data output terminal and outputs and inversion output data which is inverted as to said input data to said inversion data output terminal, wherein said bypass circuit includes a first bypass circuit coupled between said data input terminal and said non-inversion data output terminal, and a second bypass circuit coupled between said input terminal and said inversion data output terminal, wherein said switch means conducts said first and second bypass circuits to said non-inversion data output terminal and inversion data output terminal, respectively, when said memory circuit is in said write state, and conducts said memory circuit to said non-inversion data output terminal and inversion data output terminal when said memory circuit is in said latch state.

Claim 6

The semiconductor integrated circuit device according to claim 1, wherein said bypass circuit conducts to said data output terminal and outputs said output data to said data output terminal in response to a first level of said clock signal and is not conducted to said data output terminal and does not output said output data to said data output terminal in response to a second level of said clock signal.

Claim 7

The semiconductor integrated circuit device according to claim 5, wherein said memory circuit does not conduct to said data output terminal and does not output said output data to said data output terminal in response to said first level of said clock signal and conducts said output data to said output data terminal in response to said second level of said clock signal.

Claim 8

The semiconductor integrated circuit device according to claim 1, wherein said semiconductor integrated circuit device is a microcomputer.

Claim 9

The semiconductor integrated circuit device according to claim 4, wherein said first bypass circuit conducts to said non-inversion data output terminal and outputs said output data to said non-inversion data output terminal in response to a first level of said clock signal and does not conduct said output data to said non-inversion data output terminal in response to a second level of said clock signal, and wherein said second bypass circuit conducts said output data to said inversion data output terminal in response to said first level of said clock signal and does not conduct said output data to said inversion data output terminal in response to said second level of said clock signal.

Claim 10

The semiconductor integrated circuit device according to claim 1 wherein said memory means is formed using a unit cell wherein wiring lines are made by means of design automation.

Claim 11

The semiconductor integrated circuit device according to claim 8, wherein said memory circuit conducts said output data to said non-inversion data output terminal in response to said first level of said clock signal and does not conduct said output data to said non-inversion data output terminal in response to said second level of said clock signal, and wherein said memory circuit conducts said output data to said inversion data output terminal in response to said first level of said clock signal and does not conduct said output data to said inversion data output terminal in response to said second level of said clock signal.

Claim 12

A semiconductor integrated circuit device having its logical operation timing controlled by a clock synchronization and having a memory means, wherein said memory means comprises: a data input terminal to which input data is inputted; a data output terminal from which output data is outputted from said memory means; a memory circuit, in which said input data is latched statically, coupled between said data input terminal and said data output terminal and having first gate stages coupled in series between said data input terminal and data output terminal; a bypass circuit coupled in parallel to said memory circuit and having second gate stages coupled in series between said input terminal and said output terminal; and, switch means for conducting said input data through the bypass circuit to said data output terminal when said memory circuit is in a write state, and for conducting said input data through the memory circuit to said data output terminal when said memory circuit is in a latch state, wherein said switch means is controlled by a clock signal supplied from outside said memory means, wherein said memory circuit has a first propagation delay time of a first value to propagate said input data from said data input terminal to said data output terminal through said first gate stages, wherein said bypass circuit has a second propagation delay time of a second value to propagate said input data from said data input terminal to said data output terminal through said second gate stages, wherein said second value is smaller than said first value, wherein said bypass circuit has a high level setting means for setting a high level to said data output terminal and a low level setting means for setting a low level to said data output terminal, wherein said high level setting means and said low level setting means are selectively activated according to a level of said input data.

Claim 13

A semiconductor integrated circuit device having its logical operation timing controlled by a clock synchronization and having a memory means, wherein said memory means comprises: a data input terminal to which input data is inputted; a data output terminal from which output data is outputted from said memory means; a memory circuit, in which said input data is latched statically, coupled between said data input terminal and said data output terminal and having first gate stages coupled in series between said data input terminal and data output terminal; a bypass circuit coupled in parallel to said memory circuit and having second gate stages coupled in series between said input terminal and said output terminal; and, switch means for conducting said input data through the bypass circuit to said data output terminal when said memory circuit is in a write state, and for conducting said input data through the memory circuit to said data output terminal when said memory circuit is in a latch state, wherein said switch means is controlled by a clock signal supplied from outside said memory means, wherein said memory circuit has a first propagation delay time of a first value to propagate said input data from said data input terminal to said data output terminal through said first gate stages, wherein said bypass circuit has a second propagation delay time of a second value to propagate said input data from said data input terminal to said data output terminal through said second gate stages, wherein said second value is smaller than said first value, wherein said bypass circuit has a high level setting means for setting a high level to said data output terminal and a low level setting means for setting a low level to said data output terminal, wherein said high level setting means and said low level setting means are selectively activated according to a level of said input data.

Claim 14

The semiconductor integrated circuit device according to claim 11, wherein said memory circuit includes a driver circuit for driving a load to be coupled to said data output terminal and wherein a drive ability of said high level setting means and said low level setting means are substantially equal to or larger than that of said driver circuit.

Claim 15

The semiconductor integrated circuit device according to claim 11, wherein said memory circuit has a write control switch for selectively inputting said input data to said memory circuit, and wherein said write control switch is controlled by said clock signal.

Claim 16

The semiconductor integrated circuit device according to claim 11, wherein said bypass circuit conducts said output data to said data output terminal in response to a first level of said clock signal and does not conduct said output data to said data output terminal in response to a second level of said clock signal.

Claim 17

The semiconductor integrated circuit device according to claim 14, wherein said memory circuit does not conduct said output data to said data output terminal in response to said first level of said clock signal and conducts said output data to said data output terminal in response to said second level of said clock signal.

Claim 18

The semiconductor integrated circuit device according to claim 13, wherein said data output terminal includes a non-inversion data output terminal and an inversion data output terminal; wherein said memory means is coupled to both said non-inversion data output terminal and said inversion data output terminal and outputs a non-inversion output data which is not inverted as to said input data to said non-inversion data output terminal and outputs an inversion output data which is inverted as to said input data to said inversion data output terminal; wherein said bypass circuit includes a first bypass circuit coupled between said data input terminal and said non-inversion data output terminal, and a second bypass circuit coupled between said data input terminal and said inversion data output terminal; wherein said switch means conducts said output data through the first and second bypass circuits to said non-inversion data output terminal and inversion data output terminal, respectively, when said memory circuit is in said write state, and conducts said output data through said memory circuit to said non-inversion data output terminal and inversion data output terminal when said memory circuit is in said latch state.

Claim 19

The semiconductor integrated circuit device according to claim 11, wherein said semiconductor integrated circuit device is a microcomputer.

Claim 20

The semiconductor integrated circuit device according to claim 11 wherein said memory means is formed using a unit cell wherein wiring lines are made by means of design automation.

Claim 21

A semiconductor integrated circuit device having its logical operation timing controlled by a clock synchronization and having a memory means in which input data is latched statically, wherein said memory means comprises: a data input terminal to which said input data is inputted; a data output terminal from which output data is outputted from said memory means; two memory circuits of master and slave stages coupled in series between said data input terminal and said data output terminal; a bypass circuit coupled in parallel to said slave stage memory circuit, wherein said input data are written and latched statically in said master stage memory circuit, wherein a data of said master stage memory circuit is written and latched statically in said slave stage memory circuit, wherein said bypass circuit has a smaller number of gate stages in series between said data input terminal and said data output terminal than the number of gate stages in series of said slave stage memory circuit between said data input terminal and data output terminal; and, switch means for conducting said input data through the bypass circuit to said data output terminal when said slave stage memory circuit is in a write state, and for conducting said input data through the slave stage memory circuit to said data output terminal when said slave stage memory circuit is in a latch state, wherein said switch means is controlled by a clock signal, wherein said bypass circuit has a high level setting means for setting a high level to said data output terminal and a low level setting means for setting a low level to said data output terminal, wherein said high level setting means and low level setting means are selectively activated according to a level of said clock signal.

Claim 22

A semiconductor integrated circuit device having its logical operation timing controlled by a clock synchronization and having a memory means in which input data is latched statically, wherein said memory means comprises: a data input terminal to which said input data is inputted; a data output terminal from which output data is outputted from said memory means; two memory circuits of master and slave stages coupled in series between said data input terminal and said data output terminal; a bypass circuit coupled in parallel to said slave stage memory circuit, wherein said input data are written and latched statically in said master stage memory circuit, wherein a data of said master stage memory circuit is written and latched statically in said slave stage memory circuit, wherein said bypass circuit has a smaller number of gate stages in series between said data input terminal and said data output terminal than the number of gate stages in series of said slave stage memory circuit between said data input terminal and data output terminal; and, switch means for conducting said input data through the bypass circuit to said data output terminal when said slave stage memory circuit is in a write state, and for conducting said input data through the slave stage memory circuit to said data output terminal when said slave stage memory circuit is in a latch state, wherein said switch means is controlled by a clock signal, wherein said bypass circuit has a high level setting means for setting a high level to said data output terminal and a low level setting means for setting a low level to said data output terminal, wherein said high level setting means and low level setting means are selectively activated according to a level of said clock signal.

Claim 23

The semiconductor integrated circuit device according to claim 11, wherein said slave stage memory circuit includes a driver circuit for driving a load to be coupled to said data output terminal, wherein a drive ability of said high level setting means and low level setting means are substantially equal to or larger than that of said driver circuit.

Claim 24

The semiconductor integrated circuit device according to claim 11, wherein said bypass circuit conducts said output data to said data output terminal in response to a first level of said clock signal and does not conduct said output data to said data output terminal in response to a second level of said clock signal.

Claim 25

The semiconductor integrated circuit device according to claim 21, wherein said slave stage memory circuit does not conduct said output data to said data output terminal in response to said first level of said clock signal and conducts said output data to said data output terminal in response to said second level of said clock signal.

Claim 26

The semiconductor integrated circuit device according to claim 19, wherein said semiconductor integrated circuit device is a microcomputer.

Claim 27

The semiconductor integrated circuit device according to claim 19, wherein said memory means is formed using a unit cell wherein wiring lines are made by means of design automation.

Claim 28

The semiconductor integrated circuit device according to claim 19, wherein said slave stage memory circuit has a write control switch for selectively inputting said data from said master stage memory circuit to said slave stage memory circuit or not, and wherein said write control switch is controlled by said clock signal.