Patent US5227320A successfully refreshed from Google Patents.
US5227320A
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Method for producing gate overlapped lightly doped drain (goldd) structure for submicron transistor
Assignee: Philips Semiconductors Inc
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Filing: 1991-09-10
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Granted: 1993-07-13
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Expires: 2011-09-10
Abstract
Abstract A method produces a transistor with an overlapping gate. A first gate region is placed on a substrate between two source/drain regions. The first gate region includes a polysilicon region on top of a dielectric region. Gate overlap regions are placed around the polysilicon region. The gate overlap regions extend out over the two source/drain regions. The gate overlap regions are formed of a metal-silicide layer, for example Titanium-silicide. A top portion of the metal-silicide layer is oxidized to form a silicon dioxide layer on top of the metal-silicide layer. At the time of oxidation, the metal-silicide layer is also annealed to which further helps to improves the Titanium-silicide stoichiometry.
Inventors
- 👤 Eric A. Johnson
- 👤 Ying T. Loh
- 👤 Yoshiko H. Strunk
- 👤 Chung S. Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:36
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D30/605
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
190 words
A method for producing a transistor with an overlapping gate region, the method comprising the steps of: (a) forming on a substrate a polysilicon region on top of a dielectric region; the polysilicon region being used as part of a gate region; (b) performing a first implant of atoms of a first conductivity type into a first area and a second area of the substrate to form two source/drain regions; (c) depositing a metal layer covering the polysilicon region, the metal layer extending out over the two source/drain regions; (d) annealing the metal layer to form a metal-silicon layer; (e) oxidizing a top portion of the metal-silicide layer to form a silicon dioxide layer on top of the metal-silicide layer to that the metal-silicide layer and the silicon dioxide layer overlap the two source/drain regions; and (f) performing a second implant of atoms of the first conductivity type in portions of the two source/drain regions which are not protected by the metal-silicide layer and the silicon dioxide layer, wherein gate overlap in the transistor is controlled by varying thickness of the metal-silicide layer and thickness of the silicon dioxide layer.
Claim 2
Independent Claim
190 words
A method for producing a transistor with an overlapping gate region, the method comprising the steps of: (a) forming on a substrate a polysilicon region on top of a dielectric region; the polysilicon region being used as part of a gate region; (b) performing a first implant of atoms of a first conductivity type into a first area and a second area of the substrate to form two source/drain regions; (c) depositing a metal layer covering the polysilicon region, the metal layer extending out over the two source/drain regions; (d) annealing the metal layer to form a metal-silicon layer; (e) oxidizing a top portion of the metal-silicide layer to form a silicon dioxide layer on top of the metal-silicide layer to that the metal-silicide layer and the silicon dioxide layer overlap the two source/drain regions; and (f) performing a second implant of atoms of the first conductivity type in portions of the two source/drain regions which are not protected by the metal-silicide layer and the silicon dioxide layer, wherein gate overlap in the transistor is controlled by varying thickness of the metal-silicide layer and thickness of the silicon dioxide layer.
Claim 3
Dependent Claim
22 words
A method as in claim 1 additionally comprising the step of: after step (d) and before step (e) annealing the metal-silicide layer.
Claim 4
Dependent Claim
15 words
A method as in claim 1 wherein the metal layer in step (c) comprises Titanium.
Claim 5
Dependent Claim
32 words
A method as in claim 1 wherein the first conductivity type is n-type, the first implant of atoms forms n - regions, and the second implant of atoms forms n + regions.
Claim 6
Dependent Claim
32 words
A method as in claim 1 wherein the first conductivity type is p-type, the first implant of atoms forms p - regions, and the second implant of atoms forms p + regions.
Claim 7
Independent Claim
190 words
A method for producing a transistor with an overlapping gate region, the method comprising the steps of: (a) forming on a substrate a polysilicon region on top of a dielectric region; the polysilicon region being used as part of a gate region; (b) performing a first implant of atoms of a first conductivity type into a first area and a second area of the substrate to form two source/drain regions; (c) depositing a Titanium layer covering the polysilicon region, the Titanium layer extending out over the two source/drain regions; and (d) annealing the Titanium layer to form a metal-silicide layer; (e) oxidizing a top portion of the metal-silicide layer to form a silicon dioxide layer on top of the metal-silicide layer so that the metal-silicide layer and the silicon dioxide layer overlap the two source/drain regions; and (f) performing an implant of atoms of a first conductivity type in portion of the two source/drain regions which are not protected by the metal-silicide layer and the silicon dioxide layer, wherein gate overlap in the transistor is controlled by varying thickness of the metal-silicide layer and thickness of the silicon dioxide layer.
Claim 8
Independent Claim
190 words
A method for producing a transistor with an overlapping gate region, the method comprising the steps of: (a) forming on a substrate a polysilicon region on top of a dielectric region; the polysilicon region being used as part of a gate region; (b) performing a first implant of atoms of a first conductivity type into a first area and a second area of the substrate to form two source/drain regions; (c) depositing a Titanium layer covering the polysilicon region, the Titanium layer extending out over the two source/drain regions; and (d) annealing the Titanium layer to form a metal-silicide layer; (e) oxidizing a top portion of the metal-silicide layer to form a silicon dioxide layer on top of the metal-silicide layer so that the metal-silicide layer and the silicon dioxide layer overlap the two source/drain regions; and (f) performing an implant of atoms of a first conductivity type in portion of the two source/drain regions which are not protected by the metal-silicide layer and the silicon dioxide layer, wherein gate overlap in the transistor is controlled by varying thickness of the metal-silicide layer and thickness of the silicon dioxide layer.
Claim 9
Dependent Claim
22 words
A method as in claim 6 additionally comprising the step of: after step (d) and before step (e), annealing the metal-silicide layer.
Claim 10
Dependent Claim
32 words
A method as in claim 6 wherein the first conductivity type is n-type the first implant of atoms forms n - regions, and the second implant of atoms forms n + regions.
Claim 11
Dependent Claim
32 words
A method as in claim 6 wherein the first conductivity type is p-type, the first implant of atoms forms p - regions, and the second implant of atoms forms p + regions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1996-07-12 | 1997-01-11 | 1997-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-12 | 2001-01-11 | 2001-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-12 | 2005-01-11 | 2005-07-13 | $7700.00 | Window Closed / Lapsed |