Duplicate tag store purge queue

Claim 1

A high speed processing system, comprising: at least one processor having memory; a synchronous bus for conveying data at least between said at least one processor and said memory at selectively clocked cycle time intervals; a plurality of cache memories in communication with at least said synchronous bus and comprising at least one instruction cache memory for operation in accordance with instruction transactions and at least one data cache memory for operation in accordance with data transactions; a plurality of tag stores comprising a first tag store responsive to said at least one instruction cache memory, for storing at least a first tag indicative of instruction contents of at least one instruction cache memory location, and a second tag store responsive to said at least one data cache memory, for storing at least a second tag indicative of operand contents of at least one data cache memory location; and a cache transfer coherency mechanism comprising at least one duplicate tag store for storing signals indicative of a copy of at least a selected one of said at least said first tag and said at least said second tag, said cache transfer coherency mechanism further comprising at least one duplicate tag store purge queue, responsive to said synchronous bus, said at least one duplicate tag store purge queue receiving and storing at least one of said signals indicative of at least said first tag and said at least said second tag which require invalidation in said at least one duplicate tag store and said at least one duplicate tag store purge queue further including a comparison mechanism for comparing signals in said duplicate tag store purge queue with signals being stored in said duplicate tag store whereby signals in said duplicate tag store purge queue matching signals being stored in said duplicate tag store are deleted from said duplicate tag store purge queue to preclude invalidation of signals which are newly allocated to said duplicate tag store.