Gettering treatment process

Claim 2

A process of a succession of steps for fabricating a MOSFET semiconductor device, having a gate structure comprising a gate oxide layer of a desired thickness and a conductive layer formed in succession on a semiconductor substrate, the process comprising: forming the gate oxide layer, of the gate structure of the MOSFET, in the desired thickness on the semiconductor substrate; disposing the substrate with the gate oxide layer formed thereon in a chlorine-containing gas atmosphere; irradiating the gate oxide layer, while disposed in the chlorine-containing gas atmosphere, with an ultraviolet light to generate chlorine radicals from the gas atmosphere, which chlorine radicals uniformly penetrate into and accordingly are uniformly contained within the gate oxide layer and thereby trap metal impurities within the gate oxide layer, the metal impurities comprising either or both mobile ions and relatively immobile heavy metals which, variously, are present in the gate oxide layer and penetrate into the gate oxide layer, variously, from the surface thereof and from the substrate after the irradiating step; and forming the conductive layer of the gate structure directly on the gate oxide layer, the chlorine radicals being uniformly contained therewithin, and without any step of increasing the thickness of the gate oxide layer to greater than the desired thickness of the gate oxide layer as formed on the semiconductor substrate.

Claim 3

A process according to claim 1, wherein said chlorine-containing gas is chlorine gas or hydrogen chloride gas.

Claim 4

A process according to claim 1, wherein said gate oxide layer is a silicon oxide thin layer.

Claim 5

A process according to claim 3, wherein said substrate is made of silicon and said gate oxide layer is formed by thermally oxidizing a surface of said silicon substrate.

Claim 6

A process according to claim 4, wherein said gate oxide layer has a thickness of 2 to 100 nm.

Claim 7

A process according to claim 1, wherein said gate oxide layer is heated to a temperature of from 100° C. to 400° C. by said ultraviolet light irradiation.

Claim 8

A process according to claim 6, wherein said ultraviolet light is irradiated from a mercury lamp or an eximer laser.

Claim 9

A process of a succession of steps for fabricating a dynamic RAM cell semiconductor device, having a capacitor structure comprising a lower electrode layer, a dielectric oxide layer of a desired thickness and an upper electrode layer formed in succession on a semiconductor substrate, the process comprising: forming the capacitor lower electrode layer on the semiconductor substrate; forming the dielectric oxide layer, of the dynamic RAM cell semiconductor device, in the desired thickness on the capacitor lower electrode layer; disposing the substrate with the dielectric oxide layer formed on the lower electrode layer, and thereby in turn on the substrate, in a chlorine-containing gas atmosphere; irradiating the dielectric oxide layer, while disposed in the chlorine-containing gas atmosphere, with an ultraviolet light to generate chlorine radicals from the gas atmosphere, which chlorine radicals uniformly penetrate into and accordingly are uniformly contained within the dielectric oxide layer and thereby trap metal impurities within the dielectric oxide layer, the metal impurities comprising either or both mobile ions and relatively immobile heavy metals which, variously, are present in the dielectric oxide layer and penetrate into the dielectric oxide layer, variously, from the surface thereof and from the substrate and the capacitor lower electrode layer after the ultraviolet light irradiating step; and forming the capacitor upper electrode layer directly on the dielectric oxide layer, the chlorine radicals being uniformly contained therewithin, and without any step of increasing the thickness of the dielectric oxide layer to greater than the desired thickness of the dielectric oxide layer as formed on the capacitor lower electrode layer.

Claim 10

A process of a succession of steps for fabricating a dynamic RAM cell semiconductor device, having a capacitor structure comprising a lower electrode layer, a dielectric oxide layer of a desired thickness and an upper electrode layer formed in succession on a semiconductor substrate, the process comprising: forming the capacitor lower electrode layer on the semiconductor substrate; forming the dielectric oxide layer, of the dynamic RAM cell semiconductor device, in the desired thickness on the capacitor lower electrode layer; disposing the substrate with the dielectric oxide layer formed on the lower electrode layer, and thereby in turn on the substrate, in a chlorine-containing gas atmosphere; irradiating the dielectric oxide layer, while disposed in the chlorine-containing gas atmosphere, with an ultraviolet light to generate chlorine radicals from the gas atmosphere, which chlorine radicals uniformly penetrate into and accordingly are uniformly contained within the dielectric oxide layer and thereby trap metal impurities within the dielectric oxide layer, the metal impurities comprising either or both mobile ions and relatively immobile heavy metals which, variously, are present in the dielectric oxide layer and penetrate into the dielectric oxide layer, variously, from the surface thereof and from the substrate and the capacitor lower electrode layer after the ultraviolet light irradiating step; and forming the capacitor upper electrode layer directly on the dielectric oxide layer, the chlorine radicals being uniformly contained therewithin, and without any step of increasing the thickness of the dielectric oxide layer to greater than the desired thickness of the dielectric oxide layer as formed on the capacitor lower electrode layer.

Claim 11

A process according to claim 8, wherein said chlorine-containing gas is chlorine gas or hydrogen chloride gas.

Claim 12

A process according to claim 8, wherein said dielectric oxide layer is a silicon oxide thin layer.

Claim 13

A process according to claim 10, wherein said substrate is formed of silicon and said silicon oxide thin layer is formed by thermally oxidizing a surface of said silicon substrate.

Claim 14

A process according to claim 11, wherein said silicon oxide thin layer has a thickness of from 2 to 100 nm.

Claim 15

A process according to claim 8, wherein said dielectric oxide layer is heated to a temperature of from 100° C. to 400° C. by said ultraviolet irradiation.

Claim 16

A process according to claim 13, wherein said ultraviolet light is irradiated from a mercury lamp or an eximer laser.

Claim 17

A process of a succession of steps for fabricating a MOSFET semiconductor device, having a gate structure comprising a gate oxide layer of a thickness selected in accordance with the desired characteristics of the MOS semiconductor device and a conductive layer formed in succession on a main surface of the semiconductor substrate, the process comprising: forming the gate oxide layer, of the gate structure of the MOSFET, in the desired thickness on the main surface of the semiconductor substrate, the gate oxide layer having an exposed main surface displaced from the main surface of the semiconductor substrate by the selected thickness of the gate oxide layer; disposing the substrate with the gate oxide layer, as formed in the selected thickness on the main surface of the substrate, in a chlorine-containing gas atmosphere; irradiating the gate oxide layer, while disposed in the chlorine-containing gas atmosphere, with an ultraviolet light to generate chlorine radicals from the gas atmosphere, which chlorine radicals uniformly penetrate into and accordingly are uniformly contained within the gate oxide layer and thereby trap metal impurities within the gate oxide layer, the metal impurities comprising either or both mobile ions and relatively immobile heavy metals which, variously, are present in the gate oxide layer and penetrate into the gate oxide layer, variously, from the surface thereof and from the substrate after the ultraviolet light irradiating step; and forming the conductive layer of the gate structure directly on the exposed main surface of the gate oxide layer of the selected thickness and having the chlorine radicals uniformly contained therewithin, and without altering the selected thickness of the gate oxide layer.

Claim 18

A process of a succession of steps for fabricating a MOSFET semiconductor device, having a gate structure comprising a gate oxide layer of a thickness selected in accordance with the desired characteristics of the MOS semiconductor device and a conductive layer formed in succession on a main surface of the semiconductor substrate, the process comprising: forming the gate oxide layer, of the gate structure of the MOSFET, in the desired thickness on the main surface of the semiconductor substrate, the gate oxide layer having an exposed main surface displaced from the main surface of the semiconductor substrate by the selected thickness of the gate oxide layer; disposing the substrate with the gate oxide layer, as formed in the selected thickness on the main surface of the substrate, in a chlorine-containing gas atmosphere; irradiating the gate oxide layer, while disposed in the chlorine-containing gas atmosphere, with an ultraviolet light to generate chlorine radicals from the gas atmosphere, which chlorine radicals uniformly penetrate into and accordingly are uniformly contained within the gate oxide layer and thereby trap metal impurities within the gate oxide layer, the metal impurities comprising either or both mobile ions and relatively immobile heavy metals which, variously, are present in the gate oxide layer and penetrate into the gate oxide layer, variously, from the surface thereof and from the substrate after the ultraviolet light irradiating step; and forming the conductive layer of the gate structure directly on the exposed main surface of the gate oxide layer of the selected thickness and having the chlorine radicals uniformly contained therewithin, and without altering the selected thickness of the gate oxide layer.

Claim 19

A process as recited in claim 15, wherein the selected thickness of the gate oxide layer is in the range of from 2 nm to 100 nm.

Claim 20

A process as recited in claim 16, wherein the selected thickness of the gate oxide layer is approximately 20 nm.

Claim 21

A process of a succession of steps for fabricating a dynamic RAM cell semiconductor device, having a capacitor structure comprising a lower electrode layer, a dielectric oxide layer of a thickness selected in accordance with the desired characteristics of the dynamic RAM cell semiconductor device and an upper electrode layer formed in succession on a main surface of a semiconductor substrate, the process comprising: forming the capacitor lower electrode layer on the main surface of the semiconductor substrate, the capacitor lower electrode layer having an exposed, first main surface; forming the dielectric oxide layer, of the capacitor structure of the dynamic RAM cell semiconductor device, in the selected thickness and on the exposed, first main surface of the capacitor lower electrode layer, the dielectric oxide layer having an exposed main surface displaced from the first main surface of the capacitor lower electrode layer by the selected thickness of the dielectric oxide layer; disposing the substrate with the dielectric oxide layer, as formed in the selected thickness on the first main surface of the lower electrode layer in turn formed on the main surface of the substrate, in a chlorine-containing gas atmosphere; irradiating the dielectric oxide layer, while disposed in the chlorine-containing gas atmosphere, with an ultraviolet light to generate chlorine radicals from the gas atmosphere, which chlorine radicals uniformly penetrate into and accordingly are uniformly contained within the dielectric oxide layer and trap metal impurities within the dielectric oxide layer, the metal impurities comprising either or both mobile ions and relatively immobile heavy metals which, variously, are present in the dielectric oxide layer and penetrate into the dielectric oxide layer, variously, from the surface thereof and from the substrate and the capacitor lower electrode layer after the ultraviolet light irradiating step; and forming the capacitor upper electrode layer directly on the exposed main surface of the dielectric oxide layer of the selected thickness and having the chlorine radicals uniformly contained therewithin, and without altering the selected thickness of the dielectric oxide layer.

Claim 22

A process of a succession of steps for fabricating a dynamic RAM cell semiconductor device, having a capacitor structure comprising a lower electrode layer, a dielectric oxide layer of a thickness selected in accordance with the desired characteristics of the dynamic RAM cell semiconductor device and an upper electrode layer formed in succession on a main surface of a semiconductor substrate, the process comprising: forming the capacitor lower electrode layer on the main surface of the semiconductor substrate, the capacitor lower electrode layer having an exposed, first main surface; forming the dielectric oxide layer, of the capacitor structure of the dynamic RAM cell semiconductor device, in the selected thickness and on the exposed, first main surface of the capacitor lower electrode layer, the dielectric oxide layer having an exposed main surface displaced from the first main surface of the capacitor lower electrode layer by the selected thickness of the dielectric oxide layer; disposing the substrate with the dielectric oxide layer, as formed in the selected thickness on the first main surface of the lower electrode layer in turn formed on the main surface of the substrate, in a chlorine-containing gas atmosphere; irradiating the dielectric oxide layer, while disposed in the chlorine-containing gas atmosphere, with an ultraviolet light to generate chlorine radicals from the gas atmosphere, which chlorine radicals uniformly penetrate into and accordingly are uniformly contained within the dielectric oxide layer and trap metal impurities within the dielectric oxide layer, the metal impurities comprising either or both mobile ions and relatively immobile heavy metals which, variously, are present in the dielectric oxide layer and penetrate into the dielectric oxide layer, variously, from the surface thereof and from the substrate and the capacitor lower electrode layer after the ultraviolet light irradiating step; and forming the capacitor upper electrode layer directly on the exposed main surface of the dielectric oxide layer of the selected thickness and having the chlorine radicals uniformly contained therewithin, and without altering the selected thickness of the dielectric oxide layer.

Claim 23

A process as recited in claim 18, wherein the selected thickness of the dielectric oxide layer is in the range of from 2 nm to 100 nm.

Claim 24

A process as recited in claim 19, wherein the selected thickness of the dielectric oxide layer is approximately 20 nm.

Claim 25

A process of a succession of steps for fabricating a MOSFET semiconductor device, having a gate structure comprising a gate oxide layer and a conductive layer, on a semiconductor substrate, the process comprising: forming the gate oxide layer of the gate structure of the MOSFET, the gate oxide layer being of a desired thickness; disposing the substrate with the gate oxide layer formed thereon in a chlorine-containing gas atmosphere; irradiating the gate oxide layer, while disposed in the chlorine-containing gas atmosphere, with an ultraviolet light to generate chlorine radicals from the gas atmosphere, which chlorine radicals penetrate into and uniformly disperse within, and thereby trap metal impurities within, the gate oxide layer, the metal impurities comprising either or both mobile ions and relatively immobile heavy metals which, variously, are present in the gate oxide layer and penetrate into the gate oxide layer variously from the surface thereof and from the substrate after the irradiating step; and forming the conductive layer of the gate structure directly on the gate oxide layer while maintaining the chlorine radicals uniformly dispersed therewithin and without increasing the desired thickness of the gate oxide layer.

Claim 26

A process of a succession of steps for fabricating a MOSFET semiconductor device, having a gate structure comprising a gate oxide layer and a conductive layer, on a semiconductor substrate, the process comprising: forming the gate oxide layer of the gate structure of the MOSFET, the gate oxide layer being of a desired thickness; disposing the substrate with the gate oxide layer formed thereon in a chlorine-containing gas atmosphere; irradiating the gate oxide layer, while disposed in the chlorine-containing gas atmosphere, with an ultraviolet light to generate chlorine radicals from the gas atmosphere, which chlorine radicals penetrate into and uniformly disperse within, and thereby trap metal impurities within, the gate oxide layer, the metal impurities comprising either or both mobile ions and relatively immobile heavy metals which, variously, are present in the gate oxide layer and penetrate into the gate oxide layer variously from the surface thereof and from the substrate after the irradiating step; and forming the conductive layer of the gate structure directly on the gate oxide layer while maintaining the chlorine radicals uniformly dispersed therewithin and without increasing the desired thickness of the gate oxide layer.

Claim 27

A process as recited in claim 21, wherein the selected thickness of the gate oxide layer is in the range of from 2 nm to 100 nm.

Claim 28

A process as recited in claim 22, wherein the selected thickness of the gate oxide layer is approximately 20 nm.

Claim 29

A process of a succession of steps for fabricating a dynamic RAM cell semiconductor device, having a capacitor structure comprising a lower electrode layer, a dielectric oxide layer and an upper electrode layer, on a semiconductor substrate, the process comprising: forming the capacitor lower electrode layer on the semiconductor substrate; forming the dielectric oxide layer in a desired thickness on the capacitor lower electrode layer disposing the substrate with the dielectric oxide layer formed on the lower electrode layer, and thereby in turn on the substrate, in a chlorine-containing gas atmosphere; irradiating the dielectric oxide layer, while disposed in the chlorine-containing gas atmosphere, with an ultraviolet light to generate chlorine radicals from the gas atmosphere, which chlorine radicals penetrate into and uniformly disperse within, and thereby trap metal impurities within, the dielectric oxide layer, the metal impurities comprising either or both mobile ions and relatively immobile heavy metals which, variously, are present in the dielectric oxide layer and penetrate into the dielectric oxide layer variously from the surface thereof and from the substrate and the capacitor lower electrode layer after the ultraviolet light irradiating step; and forming the capacitor upper electrode layer directly on the dielectric oxide layer while maintaining the chlorine radicals uniformly dispersed therewithin and without increasing the desired thickness of the dielectric oxide layer.

Claim 30

A process of a succession of steps for fabricating a dynamic RAM cell semiconductor device, having a capacitor structure comprising a lower electrode layer, a dielectric oxide layer and an upper electrode layer, on a semiconductor substrate, the process comprising: forming the capacitor lower electrode layer on the semiconductor substrate; forming the dielectric oxide layer in a desired thickness on the capacitor lower electrode layer disposing the substrate with the dielectric oxide layer formed on the lower electrode layer, and thereby in turn on the substrate, in a chlorine-containing gas atmosphere; irradiating the dielectric oxide layer, while disposed in the chlorine-containing gas atmosphere, with an ultraviolet light to generate chlorine radicals from the gas atmosphere, which chlorine radicals penetrate into and uniformly disperse within, and thereby trap metal impurities within, the dielectric oxide layer, the metal impurities comprising either or both mobile ions and relatively immobile heavy metals which, variously, are present in the dielectric oxide layer and penetrate into the dielectric oxide layer variously from the surface thereof and from the substrate and the capacitor lower electrode layer after the ultraviolet light irradiating step; and forming the capacitor upper electrode layer directly on the dielectric oxide layer while maintaining the chlorine radicals uniformly dispersed therewithin and without increasing the desired thickness of the dielectric oxide layer.

Claim 31

A process as recited in claim 24, wherein the selected thickness of the dielectric oxide layer is in the range of from 2 nm to 100 nm.

Claim 32

A process as recited in claim 25, wherein the selected thickness of the dielectric oxide layer is approximately 20 nm.