Address translation in fft numerical data processor

Claim 2

A fast Fourier transform (FFT) numerical data processor comprising memory means for holding 4 n data at a plurality of addresses, an address bus and a data bus connected to said memory means for reading data out of and writing data into said memory means at said plurality of addresses, first and second registers connected to said data bus for receiving and holding data from said memory means, multiplier means for receiving said data held in said first and second registers and for multiplying said data held in said first register by said data held in said second register, addition/integration means for receiving an output from said multiplier means and for performing an addition/integration of the output of the multiplier means, said addition/integration means having an output connected to said data bus so that a result is transferred to said memory means, translated address generation means coupled to the address bus for generating a translation address corresponding to the base number 4 for translation of an address of the data to be supplied to said first and second registers from said memory means, and controller means for controlling said memory means, said first and second registers and the translated address generating means in a programmed manner so that a fast Fourier transform is executed by performing 4 n /4×log 4 4 n butterfly operations.

Claim 3

A fast Fourier transform (FFT) numerical data processor comprising memory means for holding 4 n ×2 m data at a plurality of addresses, an address bus and a data bus connected to said memory means for reading data out of and writing data into said memory means at said plurality of addresses, first and second registers connected to said data bus for receiving and holding data from said memory means, multiplier means for receiving said data held in said first and second registers and for multiplying said data held in said first register by said data held in said second register, addition/integration means for receiving an output from said multiplier means and for performing an addition/integration of the output of the multiplier means, said addition/integration means having an output connected to said data bus so that a result is transferred to said memory means, first translated address generation means coupled to the address bus for generating a translation address corresponding to the base number 4 for translation of an address of the data to be supplied to said first and second registers from said memory means, second translated address generating means coupled to the address bus for generating a translation address corresponding to the base number 2 for translation of an address of the input data to be supplied to said first and second register means from said memory means, and controller means for controlling said memory means, said first and second registers and said first and said second translated address generation means in a programmed manner so that a fast Fourier transform is executed by performing 4 n /4×log 4 4 n +2 m /2×log 2 2 m butterfly operations.

Claim 4

A fast Fourier transform (FFT) numerical data processor comprising memory means for holding 4 n ×2 m data at a plurality of addresses, an address bus and a data bus connected to said memory means for reading data out of and writing data into said memory means at said plurality of addresses, first and second registers connected to said data bus for receiving and holding data from said memory means, multiplier means for receiving said data held in said first and second registers and for multiplying said data held in said first register by said data held in said second register, addition/integration means for receiving an output from said multiplier means and for performing an addition/integration of the output of the multiplier means, said addition/integration means having an output connected to said data bus so that a result is transferred to said memory means, first translated address generation means coupled to the address bus for generating a translation address corresponding to the base number 4 for translation of an address of the data to be supplied to said first and second registers from said memory means, second translated address generating means coupled to the address bus for generating a translation address corresponding to the base number 2 for translation of an address of the input data to be supplied to said first and second register means from said memory means, and controller means for controlling said memory means, said first and second registers and said first and said second translated address generation means in a programmed manner so that a fast Fourier transform is executed by performing 4 n /4×log 4 4 n +2 m /2×log 2 2 m butterfly operations.