US3777131A — High base multiple rail fourier transform serial …

Claim 1

Independent Claim 234 words

A processor having parallel and serial processor sections for a Fast Fourier Transform (FFT) machine using expansion bases higher than 2 for the implementation of the Cooley-Tukey algorithm comprising: first and second sequentially connected serial processor stages for input data, each of the first and second serial processor stages having: a plurality of input and output means equal in number to the expansion base thereof, alignment means connected to the plurality of input means to align the input data in a predetermined position, means connected to the output of the alignment means to arrange an entire integration period of the data in parallel, multiplier means connected to the last recited means and receiving variable phase shift multiplying angle inputs to provide the proper phase shift for the parallel data in accordance with the algorithm, and a summing circuit connected to receive the output of the multiplier means and including constant phase shift means to generate outputs at the output means in accordance with the algorithm; the parallel processor section having a number of output means equal to its base expansion number, and wherein the input means of the first serial processor stage is connected to the output means of the parallel processor section, and the input means of the second serial processor stage is connected to the output means of the first serial processor stage to receive as input data the generated outputs therefrom.

Claim 2

Dependent Claim 234 words

A processor having parallel and serial processor sections for a Fast Fourier Transform (FFT) machine using expansion bases higher than 2 for the implementation of the Cooley-Tukey algorithm comprising: first and second sequentially connected serial processor stages for input data, each of the first and second serial processor stages having: a plurality of input and output means equal in number to the expansion base thereof, alignment means connected to the plurality of input means to align the input data in a predetermined position, means connected to the output of the alignment means to arrange an entire integration period of the data in parallel, multiplier means connected to the last recited means and receiving variable phase shift multiplying angle inputs to provide the proper phase shift for the parallel data in accordance with the algorithm, and a summing circuit connected to receive the output of the multiplier means and including constant phase shift means to generate outputs at the output means in accordance with the algorithm; the parallel processor section having a number of output means equal to its base expansion number, and wherein the input means of the first serial processor stage is connected to the output means of the parallel processor section, and the input means of the second serial processor stage is connected to the output means of the first serial processor stage to receive as input data the generated outputs therefrom.

Claim 3

Dependent Claim 15 words

A processor as recited in claim 1 wherein the alignment means comprise first delay means.

Claim 4

Dependent Claim 20 words

A processor as recited in claim 2 wherein the means to arrange the data in parallel comprise second delay means.

Claim 5

Dependent Claim 18 words

A processor as recited in claim 3 wherein the first and second delay means comprise interacting register means.

Claim 6

Dependent Claim 78 words

A processor as recited in claim 1 wherein the parallel processor section has a base expansion number and number of output means twice that of the base expansion number and number of input means of the sequentially connected first and second serial processor stages, and further comprising: additional sequentially connected first and second serial processor stages, the input means of the first additional serial processor stage being connected to the remaining output means of the parallel processor stage.

Claim 7

Dependent Claim 44 words

A processor as recited in claim 1 wherein the base expansion number and number of output means of the parallel processor section is equal to the base expansion number and number of input and output means of the first and second serial processor stages.

Claim 8

Dependent Claim 150 words

A serial processor for a Fast Fourier Transform (FFT) machine using expansion bases higher than 2 for the implementation of the Cooley-Tukey algorithm comprising: at least one serial processor stage for input data having a plurality of input and output means equal in number to the expansion base of the serial processor, alignment means connected to the plurality of input means to align the input data in a predetermined position, means connected to the output of the alignment means to arrange an entire integration period of the data in parallel, multiplier means connected to the last recited means having variable shift multiplying angles associated therewith to provide the proper phase shift for the parallel data in accordance with the algorithm, a summing circuit connected to receive the output of the multiplier means and including constant phase shift means to generate outputs at the output means in accordance with the algorithm.

Claim 9

Dependent Claim 150 words

A serial processor for a Fast Fourier Transform (FFT) machine using expansion bases higher than 2 for the implementation of the Cooley-Tukey algorithm comprising: at least one serial processor stage for input data having a plurality of input and output means equal in number to the expansion base of the serial processor, alignment means connected to the plurality of input means to align the input data in a predetermined position, means connected to the output of the alignment means to arrange an entire integration period of the data in parallel, multiplier means connected to the last recited means having variable shift multiplying angles associated therewith to provide the proper phase shift for the parallel data in accordance with the algorithm, a summing circuit connected to receive the output of the multiplier means and including constant phase shift means to generate outputs at the output means in accordance with the algorithm.

Claim 10

Dependent Claim 16 words

A serial processor as recited in claim 7 wherein the alignment means comprise first delay means.

Claim 11

Dependent Claim 21 words

A serial processor as recited in claim 8 wherein the means to arrange the data in parallel comprise second delay means.

Claim 12

Dependent Claim 19 words

A serial processor as recited in claim 9 wherein the first and second delay means comprise interacting register means.

Claim 13

Dependent Claim 34 words

A serial processor as recited in claim 7 connected to receive the output of a parallel processor section, the parallel processor section having a number of output means equal to the base expansion number.

Claim 14

Dependent Claim 180 words

A serial processor stage for a Fast Fourier Transform machine using an expansion base higher than 2 for the implementation of the Cooley-Tukey algorithm comprising: input means for converting a succession of input samples of a desired integration period including a predetermined number of samples into a plurality of successive groups of equal numbers of samples, and presenting the corresponding samples of said groups in parallel, a multiplier section for receiving the plural groups of samples from said input means and producing a corresponding number of plural parallel outputs, a summing section receiving the parallel outputs of said multiplier section and producing a corresponding number of plural parallel outputs, said summing section including a plurality of summers and means for multiplying selected ones of said samples by constant phase shifts in accordance with the algorithm, and said multiplier section including multipliers for multiplying selected ones of the samples by variable phase shifts whereby the phase shifts of samples produced through said multiplier and summing sections, and the summing of samples by said summing means, are in accordance with the algorithm.

Claim 15

Dependent Claim 180 words

A serial processor stage for a Fast Fourier Transform machine using an expansion base higher than 2 for the implementation of the Cooley-Tukey algorithm comprising: input means for converting a succession of input samples of a desired integration period including a predetermined number of samples into a plurality of successive groups of equal numbers of samples, and presenting the corresponding samples of said groups in parallel, a multiplier section for receiving the plural groups of samples from said input means and producing a corresponding number of plural parallel outputs, a summing section receiving the parallel outputs of said multiplier section and producing a corresponding number of plural parallel outputs, said summing section including a plurality of summers and means for multiplying selected ones of said samples by constant phase shifts in accordance with the algorithm, and said multiplier section including multipliers for multiplying selected ones of the samples by variable phase shifts whereby the phase shifts of samples produced through said multiplier and summing sections, and the summing of samples by said summing means, are in accordance with the algorithm.

Claim 16

Dependent Claim 97 words

A serial processor stage as recited in claim 12 wherein said input means includes switching means, and storing means having a number of inputs corresponding to the number of groups, said switching means supplies said groups of samples to said inputs of said storing means, in succession, and said storing means includes individual storing means of selected, different storage time periods connected to said inputs for receiving and storing respectively associated ones of said groups of samples for different time periods so as to present the corresponding samples of said groups in parallel to said multiplier section.

Claim 17

Dependent Claim 33 words

A serial processor stage as recited in claim 12 wherein: said multipliers of said multiplier section receive corresponding ones of said groups of samples and variable phase shift inputs Wm in accordance with

Claim 18

Dependent Claim 41 words

A serial processor stage as recited in claim 12 wherein said constant phase shift multiplier of said summing section performs phase shifting in accordance with phase shift angles having a smallest increment of 360* divided by the base of the stage.

Claim 19

Dependent Claim 41 words

A serial processor stage as recited in claim 15 and implemented for a base 4 expansion, wherein the constant phase shift multiplier of said summing section performs phase shifting in accordance with phase shift angles having a smallest increment of 90*.

Claim 20

Dependent Claim 25 words

A serial processor stage as recited in claim 16 whErein said summing section includes a single 90* phase shifter as the constant phase angle multiplier.

Claim 21

Dependent Claim 41 words

A serial processor stage as recited in claim 15 and implemented for a base 8 expansion, wherein the constant phase shift multiplier of said summing section performs phase shifting in accordance with phase shift angles having a smallest increment of 45*.

Claim 22

Dependent Claim 26 words

A serial processor stage as recited in claim 18 wherein said summing section includes 45*, 90* and 135* phase shifters as the constant phase angle multipliers.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1976-12-03	1977-06-04	1977-12-04	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1980-12-03	1981-06-04	1981-12-04	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1984-12-03	1985-06-04	1985-12-04	$7700.00	Window Closed / Lapsed

High base multiple rail fourier transform serial stage

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