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US4630229A Expired / Lapsed US ⏱️ 0.0 years remaining

Circuit for the fast calculation of the discrete Fourier transform of a signal

Assignee: Intercontrole SA
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Filing: 1983-02-18
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Granted: 1986-12-16
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Expires: 2003-02-18
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Abstract

Abstract A circuit for the rapid calculation of the real and imaginary parts of the h first harmonics of a signal supplied by a measuring device and particularly for the analysis of the voltage supplied by a non-destructive eddy current testing probe. The circuit comprises an analog-digital converter, a random access memory, and calculating means comprising a PROM, a counter, a multiplier, an accumulator and a sequencer.

Inventors

  • 👤 Jean-Pierre D'Hondt

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 16:15
CPC Classifications
G; G01; G01N; G01N27/00; G01N27/72; G01N27/82; G01N27/90; G01N27/9046; G06; G06F; G06F17/00; G06F17/10; G06F17/14; G06F17/141

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 404 words
A circuit for the rapid calculation of the real and imaginary parts of the h first harmonics, h being 3 at most, of a signal supplied by a measuring device, particularly a non-destructive eddy-current testing device, said circuit comprising: an analog-digital converter having an input receiving the signal to be processed and an output supplying digital samples, a random access, acquisition memory having a data input connected to the output of the converter, an addressing input and a data output, means for calculating the discrete Fourier transform having an input connected to the output of the acquisition memory and an output supplying the real part and the imaginary part of the harmonics of the signal, said means for calculating the discrete Fourier transform comprising: a programmable read-only, coefficient memory having an addressing input and a data input, said coefficient memory being subdivided into h blocks, the kth block, with k integer between l and h, containing the coefficients sin 2πnk/N and cos 2πnk/N, in which N is the number of samples contained in the acquisition memory and in which n assumes all the values ranging from 0 to N-1, a counter having two outputs carrying two sets of addresses, the first output being connected to the addressing input of the acquisition memory and the second to the addressing input of the coefficient memory, said addresses respectively corresponding to the samples of the acquisition memory and to the coefficients of a coefficient memory block, a multiplier circuit having two inputs, one connected to the output of the acquisition memory, the other connected to the output of the coefficient memory, and an output, an accumulator circuit having an input connected to the output of the multiplier circuit and an output carrying the sought real and imaginary parts, a sequencer circuit able to transmit pulses to the counter, to control the reading of the samples in the acquisition memory and, simultaneously, the reading in the first block of the coefficient memory of the coefficients cos 2πn/N, and then to against control the reading of the samples in the acquisition memory and simultaneously the reading in the first block of the coefficient memory of coefficients sin 2πn/N and, for each reading of the sample and a coefficient, to control the multiplier and then the accumulator and then reiterate the controlling and reading with the second block of the coefficient memory and so on up to the last block.
Claim 2
Dependent Claim 404 words
A circuit for the rapid calculation of the real and imaginary parts of the h first harmonics, h being 3 at most, of a signal supplied by a measuring device, particularly a non-destructive eddy-current testing device, said circuit comprising: an analog-digital converter having an input receiving the signal to be processed and an output supplying digital samples, a random access, acquisition memory having a data input connected to the output of the converter, an addressing input and a data output, means for calculating the discrete Fourier transform having an input connected to the output of the acquisition memory and an output supplying the real part and the imaginary part of the harmonics of the signal, said means for calculating the discrete Fourier transform comprising: a programmable read-only, coefficient memory having an addressing input and a data input, said coefficient memory being subdivided into h blocks, the kth block, with k integer between l and h, containing the coefficients sin 2πnk/N and cos 2πnk/N, in which N is the number of samples contained in the acquisition memory and in which n assumes all the values ranging from 0 to N-1, a counter having two outputs carrying two sets of addresses, the first output being connected to the addressing input of the acquisition memory and the second to the addressing input of the coefficient memory, said addresses respectively corresponding to the samples of the acquisition memory and to the coefficients of a coefficient memory block, a multiplier circuit having two inputs, one connected to the output of the acquisition memory, the other connected to the output of the coefficient memory, and an output, an accumulator circuit having an input connected to the output of the multiplier circuit and an output carrying the sought real and imaginary parts, a sequencer circuit able to transmit pulses to the counter, to control the reading of the samples in the acquisition memory and, simultaneously, the reading in the first block of the coefficient memory of the coefficients cos 2πn/N, and then to against control the reading of the samples in the acquisition memory and simultaneously the reading in the first block of the coefficient memory of coefficients sin 2πn/N and, for each reading of the sample and a coefficient, to control the multiplier and then the accumulator and then reiterate the controlling and reading with the second block of the coefficient memory and so on up to the last block.
Claim 3
Dependent Claim 72 words
A circuit according to claim 1, comprising, connected to the accumulator output, a mathematical calculation microprocessor able to perform the following operations: raising to the square of the real and imaginary parts received from the accumulator, addition of the squares obtained, extraction of the square root from the sum obtained, calculation of the quotient of the imaginary part by the real part, and calculation of the arc tangent of the quotient obtained.
Claim 4
Dependent Claim 27 words
A circuit according to claim 1, comprising a microprocessor having accesses to the memories, to the counter, to the multiplier, to the accumulator and to the sequencer.
Claim 5
Dependent Claim 18 words
A circuit according to claim 1, wherein the multiplier and accumulator are constituted by the same integrated circuit.

References Cited (Backward Citations)

US3636333A Cited
US3754128A Cited
US4084251A Cited
US4117541A Cited
US4138730A Cited
US4199660A Cited
US4266279A Cited
US4334273A Cited
US4328555A Cited
US4298985A Cited
US4479229A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-12-15 1990-06-16 1990-12-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-12-15 1994-06-16 1994-12-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-12-15 1998-06-16 1998-12-16 $7700.00 Window Closed / Lapsed

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