High speed signal processor for vector transformation

Claim 2

A signal processor for transforming an input vector to an output vector which comprises: a. an input memory having an input and a plurality of at least three outputs, b. an output memory having a plurality of at least three inputs and a plurality of at least three outputs, c. an arithmetic unit having a first plurality of at least three inputs and a second plurality of inputs less by one than the first plurality of inputs and a plurality of at least three outputs, d. a weighting coefficients signal source having a plurality of at least two outputs, each connected to a corresponding one of said arithmetic unit second plurality of inputs for supplying said arithmetic unit with weighting coefficients signals, e. a signal selection means, referred to in the following as the signal selection circuitry, having a first input and a second plurality of inputs and an output, f. a control unit feeding control signals to said input memory, said output memory, said weighting coefficients signal source, and said signal selection circuitry, g. each of said input memory plurality of outputs being connected to a corresponding one of said first plurality of arithmetic unit inputs and each output of said arithmetic unit being connected to a corresponding one of said output memory plurality of inputs, h. said output memory outputs being connected to said signal selection circuitry second plurality of inputs, i. said signal selection circuitry first input being said input vector to be transformed and said signal selection circuitry output connected to said input memory input, j. said control uNit providing means for moving data in said input and output memories, for selecting one of said signal selection circuitry inputs for feeding it to said input memory input in a predetermined sequence, and for sequentially feeding selected predetermined weighting coefficients signals from said weighting coefficients signal source outputs to said arithmetic unit second plurality of inputs, k. said input memory having the form of a long queue which is divided into a plurality of at least three submemories in the form of shorter queues all connected in series, the input at the rear of the last of said submemories being said input memory input, the plurality of outputs at the fronts of the submemories are said input memory outputs, l. said output memory, of same size as said input memory, is divided into a plurality of at least three submemories having the form of equal length queues, the plurality of inputs at the rears of said submemories are said output memory inputs, and the plurality of outputs at the fronts of said output memory submemories being said output memory outputs, m. the number of said input memory submemories is equal to that of said output memory submemories, both being equal to the value of the radix of factorization of the transformation matrix which is to be multiplied by said input vector, n. said arithmetic unit plurality of outputs being, at the end of processing, the required output vector that is the result of multiplying said transformation matrix by said input vector; and wherein o. said value of the radix of factorization of the transformation matrix is restricted to be at least three.

Claim 3

In combination with a signal processor as defined in claim 1, an auxiliary output memory comprising an input and a plurality of outputs; said input of said auxiliary memory being connected to one of said outputs of said arithmetic unit; one of said outputs of said auxiliary memory being connected to a further input of said arithmetic unit; whereby the output vector is temporarily stored in said auxiliary output memory for further processing in applications requiring the performance of arithmetic operations on at least one transformed vector.

Claim 4

In combination with a signal processor as defined in claim 1, an input buffer memory for real-time on-line signal processing having input means and output means; elements of said input vector to be transformed being fed into said input buffer memory input means; said input buffer memory output means being connected to said input memory; said input vector elements being accumulated in said input buffer memory during processing of a preceding input vector by the signal processor; accumulated elements of said input vector being periodically gated from the input buffer memory into said input memory.

Claim 5

A combination as defined in claim 3, and further comprising an auxiliary output memory comprising an input and a plurality of outputs; said input of said auxiliary memory being connected to one of said outputs of said arithmetic unit; one of said outputs of said auxiliary memory being connected to a further input of said arithmetic unit; whereby the output vector is temporarily stored in said auxiliary output memory for further processing in applications requiring the performance of arithmetic operations on at least one transformed vector.

Claim 6

A signal processor for transforming an input vector to an output vector which comprises: a. an input memory having a plurality of inputs and a plurality of outputs, b. an output memory having a plurality of inputs and an output, c. an arithmetic unit having a first plurality of inputs and a second plurality of inputs equal in number to the first plurality of inputs and a plurality of outputs, d. a weighting coefficients signal source having a plurality of outputs each connected to a corresponding one of said arithmetic unit second plurality of inputs for supplying said arithmetic unit with weighting coefficients signals, e. a signal selection meaNs, referred to as the signal selection circuitry having a first and a second input and a plurality of outputs, f. a control unit feeding control signals to said input memory, to said output memory, to said weighting coefficients signal source, to said arithmetic unit, and to said signal selection circuitry, g. each of said input memory plurality of outputs being connected to a corresponding one of said first plurality of arithmetic unit inputs and each of said arithmetic unit outputs being connected to a corresponding one of said output memory plurality of inputs, h. said output memory output being connected to said signal selection circuitry second input, i. said signal selection circuitry first input being said input vector to be transformed and each of said signal selection circuitry plurality of outputs being connected to a corresponding one of said input memory plurality of inputs, j. said control unit providing means for moving data in said input and output memories, for selecting one of said signal selection circuitry inputs for feeding it to one of said input memory plurality of inputs in a predetermined sequence, for sequentially feeding selected predetermined weighting coefficients signals from said weighting coefficients signal source outputs to said arithmetic unit second plurality of inputs, and for providing signals to said arithmetic unit for bypassing predetermined arithmetic operations, k. said input memory being divided into a plurality of submemories having the form of queues, the plurality of inputs to said submemories are said input memory inputs and the plurality of outputs of said submemories are said input memory outputs, l. said output memory, having the form of a long queue, is divided into a plurality of submemories having the form of shorter queues all connected in series, the plurality of inputs to said output memory submemories are said output memory inputs, and the output at the front of the first of said output memory submemories being said output memory output , m. the number of said input memory submemories is equal to that of said output memory submemories, both being equal to the value of the radix of factorization of the transformation matrix which is to be multiplied by said input vector, n. said arithmetic unit plurality of outputs being, at the end of processing, the required output vector that is the result of multiplying said transformation matrix by said input vector; and wherein o. said value of the radix of factorization of said transformation matrix is integer.

Claim 7

A signal processor for transforming an input vector to an output vector which comprises: a. an input memory having a plurality of inputs and a plurality of outputs, b. an output memory having a plurality of inputs and an output, c. an arithmetic unit having a first plurality of inputs and a second plurality of inputs equal in number to the first plurality of inputs and a plurality of outputs, d. a weighting coefficients signal source having a plurality of outputs each connected to a corresponding one of said arithmetic unit second plurality of inputs for supplying said arithmetic unit with weighting coefficients signals, e. a signal selection meaNs, referred to as the signal selection circuitry having a first and a second input and a plurality of outputs, f. a control unit feeding control signals to said input memory, to said output memory, to said weighting coefficients signal source, to said arithmetic unit, and to said signal selection circuitry, g. each of said input memory plurality of outputs being connected to a corresponding one of said first plurality of arithmetic unit inputs and each of said arithmetic unit outputs being connected to a corresponding one of said output memory plurality of inputs, h. said output memory output being connected to said signal selection circuitry second input, i. said signal selection circuitry first input being said input vector to be transformed and each of said signal selection circuitry plurality of outputs being connected to a corresponding one of said input memory plurality of inputs, j. said control unit providing means for moving data in said input and output memories, for selecting one of said signal selection circuitry inputs for feeding it to one of said input memory plurality of inputs in a predetermined sequence, for sequentially feeding selected predetermined weighting coefficients signals from said weighting coefficients signal source outputs to said arithmetic unit second plurality of inputs, and for providing signals to said arithmetic unit for bypassing predetermined arithmetic operations, k. said input memory being divided into a plurality of submemories having the form of queues, the plurality of inputs to said submemories are said input memory inputs and the plurality of outputs of said submemories are said input memory outputs, l. said output memory, having the form of a long queue, is divided into a plurality of submemories having the form of shorter queues all connected in series, the plurality of inputs to said output memory submemories are said output memory inputs, and the output at the front of the first of said output memory submemories being said output memory output , m. the number of said input memory submemories is equal to that of said output memory submemories, both being equal to the value of the radix of factorization of the transformation matrix which is to be multiplied by said input vector, n. said arithmetic unit plurality of outputs being, at the end of processing, the required output vector that is the result of multiplying said transformation matrix by said input vector; and wherein o. said value of the radix of factorization of said transformation matrix is integer.

Claim 8

In combination with a signal processor as defined in claim 5, an auxiliary output memory comprising an input and a plurality of outputs; said input of said auxiliary memory being connected to one of said outputs of said arithmetic unit; one of said outputs of said auxiliary memory being connected to a further input of said arithmetic unit; whereby the output vector is temporarily stored in said auxiliary output memory for further processing in applications requiring the performance of arithmetic operations on at least one transformed vector.

Claim 9

In combination with a signal processor as defined in claim 5, an input buffer memory for real-time on-line signal processing having input means and output means; elements of said input vector to be transformed being fed into said input buffer memory input means; said input buffer memory output means being connected to said input memory; said input vector elements being accumulated in said input buffer memory during processing of a preceding input vector by the signal processor; accumulated elements of said input vector being periodically gated from the input buffer memory into said input memory.

Claim 10

A combination as defined in claim 7, and further comprising an auxiliary output memory comprising an input and a plurality of outputs; said input of said auxiliary memory being connected to one of said outputs of said arithmetic unit; one of said outputs of said auxiliary memory beinG connected to a further input of said arithmetic unit; whereby the output vector is temporarily stored in said auxiliary output memory for further processing in applications requiring the performance of arithmetic operations on at least one transformed vector.

Claim 11

A signal processor for transforming an input vector to an output vector which comprises: a. a first memory having a plurality of inputs and a plurality of outputs, b. a second memory having a plurality of inputs and a plurality of outputs, c. an arithmetic unit having a first and a second pluralities of inputs and a plurality of outputs, d. a weighting coefficients signal source having a plurality of outputs each connected to a corresponding one of said arithmetic unit second plurality of inputs for supplying said arithmetic unit with weighting coefficients signals, e. a first signal selection circuitry having a first and a second pluralities of inputs and a plurality of outputs, f. a second signal selection circuitry having a first and a second pluralities of inputs and a plurality of outputs, g. a control unit feeding control signals to said first memory, to said second memory, to said weighting coefficients signal source, to said arithmetic unit, and to said first and second signal selection circuitries, h. each of said first memory plurality of outputs being connected to a corresponding one of said second signal selection circuitry first plurality of inputs and each of said second memory plurality of outputs being connected to a corresponding one of said second signal selection circuitry second plurality of inputs, i. each of said second signal selection circuitry plurality of outputs being connected to a corresponding one of said arithmetic unit first plurality of inputs and each of said arithmetic unit plurality of outputs being connected to a corresponding one of each of said first signal selection circuitry second plurality of inputs and to a corresponding one of each of said second memory plurality of inputs, j. said first signal selection circuitry first plurality of inputs feed into the processor said input vector to be transformed and each of said first signal selection circuitry plurality of outputs being connected to a corresponding one of said first memory plurality of inputs, k. said control unit providing means for moving data in said first and second memories, for sequentially selecting a predetermined plurality from said first and second memories pluralities of outputs for feeding it to said arithmetic unit first plurality of inputs, for sequentially selecting a predetermined plurality from first selection circuitry first and second pluralities of inputs for feeding it to said first memory plurality of inputs, for sequentially selecting predetermined weighting coefficients signals from said weighting coefficients signal source outputs for feeding them to said arithmetic unit second plurality of inputs, and for feeding signals to said arithmetic unit for bypassing predetermined arithmetic operations, l. each of said first memory and second memory is divided into a plurality of submemories having the form of queues each of which is further divided into a plurality of shorter queues all connected in series and referred to in the following as the submemory queues, m. the plurality of inputs at the rears of said first memory submemories are said first memory inputs and the plurality of outputs at the fronts of said first memory submemory queues are said first memory plurality of outputs, n. the plurality of outputs of the submemory queues of each first memory submemory forms a subset of said first memory plurality of outputs, o. the plurality of inputs at the rears of said second memory submemories are said second memory inputs and the plurality of outputs at the fronts of said second memory submemory queues are said second memory plurality of outputs, p. the plurality of outputs of the submemory queues of each second memory sUbmemory forms a subset of said second memory plurality of outputs, q. said second signal selection circuitry being a means for selecting one subset out of the subsets of both first and second memory pluralities of outputs, r. the number of said first memory submemories is equal to that of said second memory submemories, both being equal to the value of the radix of factorization of the transformation matrix which is to be multiplied by said input vector, s. the number of submemory queues in each of said first memory submemories is equal to the number of submemory queues in each of said second memory submemories, both being equal to the value of the radix of factorization of said transformation matrix, t. said arithmetic unit plurality of outputs being, at the end of processing, the required output vector that is the result of multiplying said transformation matrix by said input vector; and wherein u. said value of the radix of factorization of said input vector is integer.

Claim 12

A signal processor for transforming an input vector to an output vector which comprises: a. a first memory having a plurality of inputs and a plurality of outputs, b. a second memory having a plurality of inputs and a plurality of outputs, c. an arithmetic unit having a first and a second pluralities of inputs and a plurality of outputs, d. a weighting coefficients signal source having a plurality of outputs each connected to a corresponding one of said arithmetic unit second plurality of inputs for supplying said arithmetic unit with weighting coefficients signals, e. a first signal selection circuitry having a first and a second pluralities of inputs and a plurality of outputs, f. a second signal selection circuitry having a first and a second pluralities of inputs and a plurality of outputs, g. a control unit feeding control signals to said first memory, to said second memory, to said weighting coefficients signal source, to said arithmetic unit, and to said first and second signal selection circuitries, h. each of said first memory plurality of outputs being connected to a corresponding one of said second signal selection circuitry first plurality of inputs and each of said second memory plurality of outputs being connected to a corresponding one of said second signal selection circuitry second plurality of inputs, i. each of said second signal selection circuitry plurality of outputs being connected to a corresponding one of said arithmetic unit first plurality of inputs and each of said arithmetic unit plurality of outputs being connected to a corresponding one of each of said first signal selection circuitry second plurality of inputs and to a corresponding one of each of said second memory plurality of inputs, j. said first signal selection circuitry first plurality of inputs feed into the processor said input vector to be transformed and each of said first signal selection circuitry plurality of outputs being connected to a corresponding one of said first memory plurality of inputs, k. said control unit providing means for moving data in said first and second memories, for sequentially selecting a predetermined plurality from said first and second memories pluralities of outputs for feeding it to said arithmetic unit first plurality of inputs, for sequentially selecting a predetermined plurality from first selection circuitry first and second pluralities of inputs for feeding it to said first memory plurality of inputs, for sequentially selecting predetermined weighting coefficients signals from said weighting coefficients signal source outputs for feeding them to said arithmetic unit second plurality of inputs, and for feeding signals to said arithmetic unit for bypassing predetermined arithmetic operations, l. each of said first memory and second memory is divided into a plurality of submemories having the form of queues each of which is further divided into a plurality of shorter queues all connected in series and referred to in the following as the submemory queues, m. the plurality of inputs at the rears of said first memory submemories are said first memory inputs and the plurality of outputs at the fronts of said first memory submemory queues are said first memory plurality of outputs, n. the plurality of outputs of the submemory queues of each first memory submemory forms a subset of said first memory plurality of outputs, o. the plurality of inputs at the rears of said second memory submemories are said second memory inputs and the plurality of outputs at the fronts of said second memory submemory queues are said second memory plurality of outputs, p. the plurality of outputs of the submemory queues of each second memory sUbmemory forms a subset of said second memory plurality of outputs, q. said second signal selection circuitry being a means for selecting one subset out of the subsets of both first and second memory pluralities of outputs, r. the number of said first memory submemories is equal to that of said second memory submemories, both being equal to the value of the radix of factorization of the transformation matrix which is to be multiplied by said input vector, s. the number of submemory queues in each of said first memory submemories is equal to the number of submemory queues in each of said second memory submemories, both being equal to the value of the radix of factorization of said transformation matrix, t. said arithmetic unit plurality of outputs being, at the end of processing, the required output vector that is the result of multiplying said transformation matrix by said input vector; and wherein u. said value of the radix of factorization of said input vector is integer.

Claim 13

In combination with a signal processor as defined in claim 9, an auxiliary output memory comprising an input and a plurality of outputs; said input of said auxiliary memory being connected to one of said outputs of said arithmetic unit; one of said outputs of said auxiliary memory being connected to a further input of said arithmetic unit; whereby the output vector is temporarily stored in said auxiliary output memory for further processing in applications requiring the performance of arithmetic operations on at least one transformed vector.

Claim 14

In combination with a signal processor as defined in claim 9, an input buffer memory for real-time on-line signal processing having input means and output means; elements of said input vector to be transformed being fed into said input buffer memory input means; said input buffer memory output being connected to said first memory; said input vector elements being accumulated in said input buffer memory during processing of a preceding input vector by the signal processor; accumulated elements of said input vector being periodically gated from the input buffer memory into said first memory.

Claim 15

A combination as defined in claim 11, and further comprising an auxiliary output memory comprising an input and a plurality of outputs; said input of said auxiliary memory being connected to one of said outputs of said arithmetic unit; one of said outputs of said auxiliary memory being connected to a further input of said arithmetic unit; whereby the output vector is temporarily stored in said auxiliary output memory for further processing in applications requiring the performance of arithmetic operations on at least one transformed vector.

Claim 16

In combination with a signal processor as defined in claim 9, an input buffer memory for real-time on-line signal processing having input means and output means; elements of said input vector to be transformed being fed into said input buffer memory input means; said input buffer memory output means being connected to said second memory; said input vector elements being accumulated in said input buffer memory during processing of a preceding input vector by the signal processor; accumulated elements of said input vector being periodically gated from the input buffer memory into said second memory.

Claim 17

A combination as defined in claim 13, and further comprising an auxiliary output memory comprising an input and a plurality of outputs; said input of said auxiliary memory being connected to one of said outputs of said arithmetic unit; one of said outputs of said auxiliary memory being connected to a further input of said arithmetic unit; whereby the output vector is temporarily stored in said auxiliary output memory for further processing in applications requiring the performance of arithmetic operations on at least one transformed vector.