Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
225 words
A circuit for producing a drive signal for starting and operating a polyphase motor having a back emf in a floating coil, comprising: a source providing an initial reference voltage; a source of clock pulses of successively decreasing periods; a voltage controlled oscillator having an input for receiving an input voltage and having a VCO output, said voltage controlled oscillator having a resynchronizing input for reinitiating said VCO output on each clock pulse of said source of clock pulses; a period comparator for comparing the period of said clock pulses to the period of said VCO output; a phase comparator for comparing the phases of the back emf and said VCO output; first, second, and third switches controlled by said period comparator; said first switch for switching the input of said voltage controlled oscillator from said initial reference voltage to said output of the phase comparator when the period of said clock pulses becomes less than the period of said VCO output; said second switch for switching from said clock pulses to said VCO output to provide said drive signal when the period of said clock pulses becomes less than the period of said VCO output; and said third switch for disabling said resynchronizing input from said clock pulses when the period of said clock signal becomes less than the period of said VCO output.
Claim 2
Dependent Claim
225 words
A circuit for producing a drive signal for starting and operating a polyphase motor having a back emf in a floating coil, comprising: a source providing an initial reference voltage; a source of clock pulses of successively decreasing periods; a voltage controlled oscillator having an input for receiving an input voltage and having a VCO output, said voltage controlled oscillator having a resynchronizing input for reinitiating said VCO output on each clock pulse of said source of clock pulses; a period comparator for comparing the period of said clock pulses to the period of said VCO output; a phase comparator for comparing the phases of the back emf and said VCO output; first, second, and third switches controlled by said period comparator; said first switch for switching the input of said voltage controlled oscillator from said initial reference voltage to said output of the phase comparator when the period of said clock pulses becomes less than the period of said VCO output; said second switch for switching from said clock pulses to said VCO output to provide said drive signal when the period of said clock pulses becomes less than the period of said VCO output; and said third switch for disabling said resynchronizing input from said clock pulses when the period of said clock signal becomes less than the period of said VCO output.
Claim 3
Dependent Claim
33 words
The circuit of claim 1 wherein said period comparator comprises flip-flop circuits to compare a positive edge of a pulse from said voltage controlled oscillator with a positive edge of said clock pulses.
Claim 4
Dependent Claim
38 words
The circuit of claim 2 wherein said flip-flop circuits operate to switch said first, second, and third switches when two positive edges of the clock pulses occur before a second positive edge from said voltage controlled oscillator occurs.
Claim 5
Dependent Claim
13 words
The circuit of claim 3 wherein said flip-flop circuits are D-type flip-flops circuits.
Claim 6
Dependent Claim
218 words
The circuit of claim 1 wherein said period comparator comprises: a first D-type flip-flop having a D input, a clock, a SET control, a RESET control, a Q output, and a Q(bar) output, wherein the D input has a reference potential impressed on it, the clock is connected to the output frequency of the voltage controlled oscillator, the SET control input is connected to an initializing control line, and the RESET control is connected to said source of clock pulses; a second D-type flip-flop having a D input, a clock, a RESET control, a Q output, and a Q(bar) output, wherein the D input is connected to the Q(bar) output of the first D-type flip-flop, the clock is connected to said source of clock pulses, and the RESET control is connected to said initializing control line; a third D-type flip-flop having a D input, a clock, a RESET control, a Q output, and a Q(bar) output, wherein the D input is connected to the Q output of the second D-type flip-flop, the RESET is connected to the initializing control line, and the Q output is connected to said first, second, and third switches; and an invertor having an input connected to the source of clock pulses and an output connected to the clock of said third D-type flip-flop.
Claim 7
Dependent Claim
10 words
The circuit of claim 1 wherein said switches are multiplexers.
Claim 8
Dependent Claim
11 words
The circuit of claim 1 wherein said switches are integrated-circuit devices.
Claim 9
Dependent Claim
24 words
The circuit of claim 1 further comprising a filter connected to an input of said voltage controlled oscillator for reducing noise and circuit overshoot.
Claim 10
Dependent Claim
13 words
The circuit of claim 8 wherein the filter is a proportional integral filter.
Claim 11
Dependent Claim
17 words
The circuit of claim 1 wherein the entire circuit is implemented on a single integrated circuit device.