Servomotor controller

Claim 2

A servomotor controller of a phase locked loop type comprising: a rotation detector arranged in association with said servomotor for outputting a phase signal corresponding to the rotation of said servomotor; a phase reference signal generating unit having a register means for storing data specifying a pulse cycle period of said phase reference signal; a phase control unit for detecting a phase difference between said phase reference signal and said output signal of said rotation detector and for outputting the detection results in numerical values; a speed reference signal generating unit having a registering means for storing data specifying a pulse width of said speed reference signal; a speed control unit which uses said speed reference signal for detecting the cycle period of said output signal of said rotation detector and for outputting the detection results in numerical values; a full adder for adding the outputs of said phase control unit and said speed control unit and for providing an output corresponding thereto; a signal converting unit for outputting a motor speed control signal corresponding to said output of said full adder; wherein said phase control unit includes a register means for storing data specifying a detectable range of phase difference with respect to the whole variation width of an output value of said phase control unit; wherein said speed control unit includes a register means for storing data specifying a detectable range of a cycle period with respect to the whole variation width of the output value of said speed control unit; and wherein said controller further comprises a controller means for providing signals for setting said register means of said phase and speed control units.

Claim 3

A servomotor controller as set forth in claim 1, wherein said phase control unit includes a circuit for thinning out a number of clock pulses determined by a thinning out part of said data from a predetermined number of clock pulses, a circuit means for frequency dividing a pulse train in an output from said thinning out circuit by a number determined by a dividing part of said data, and a counter for counting an output from said frequency dividing circuit, so that the value counted by said counter which is determined by a phase difference between said phase reference signal and said output signal of said rotation detector is used as an output of said phase control unit.

Claim 4

A servomotor controller as set forth in claim 1, wherein said speed control unit further comprises a circuit for thinning out a number clock pulses which are determined by a thinning out part of said data from a predetermined number of clock pulses, a circuit means for frequency dividing a pulse train in an output from said thinning out circuit by a number determined by a dividing part of said data, and a counter for counting an output of said frequency dividing circuit, so that the value counted by said counter which is determined by the pulse width of said speed reference signal and said output signal of said rotation detector is used as an output of said speed control unit.

Claim 5

A servomotor controller as set forth in claim 1, wherein said output of said speed control unit inverts the most significant bit thereof and inputs the inverted bit to said full adder.

Claim 6

A servomotor controller as set forth in claim 1, wherein said signal converting unit includes a pulse width modulating circuit which outputs a pulse signal of a duty ratio corresponding to the computation result of said full adder.

Claim 7

A servomotor controller as set forth in claim 5, including a logic circuit which causes said duty ratio of said pulse signal to be 1 or 0 when the computation result of said full adder is out of the predetermined range.

Claim 8

A servomotor controller as set forth in claim 1, wherein said signal converting unit includes a digital/analog converter for outputting a voltage signal corresponding to the computation result of said full adder.

Claim 9

A servomotor controller of a phase locked loop type comprising: a rotation detector arranged in association with said servomotor for outputting a pulse signal corresponding to the rotation of said servomotor; a phase reference signal generating unit having a register means for storing data specifying a pulse cycle period of said phase reference signal; a phase control unit for detecting a phase difference between said phase reference signal and said output signal of said rotation detector and for outputting the detection results in numerical values; a speed reference signal generating unit having a register means for storing data specifying a pulse width of said speed reference signal; a speed control unit which uses said speed reference signal for detecting the cycle period of said output signal of said rotation detector and for outputting the detection results in numerical values; a full adder for adding the outputs of said phase control unit and said speed control unit and for outputting data corresponding to the computational results thereof; a direct register means for storing data in connection with a motor speed control signal; a selecting circuit for selecting either data stored from said direct register means or said data output from said full adder, and a signal converting unit for outputting the motor speed control signal corresponding to the content selected by said selecting circuit; wherein said phase control unit is provided with a register means for storing data specifying a detectable range of phase difference with respect to the whole variation width of an output value of said phase control unit; wherein said speed control unit includes a register means for storing data specifying a detectable range of a cycle period with respect to the whole variation width of the output value of said speed control unit; and wherein said controller further comprises a controller means for providing signals for setting said register means of said speed and phase control unit.

Claim 10

A servomotor controller of a phase locked loop type comprising: a rotation detector arranged in association with said servomotor for outputting a pulse signal corresponding to the rotation of said servomotor; a phase reference signal generating unit having a register means for storing data specifying a pulse cycle period of said phase reference signal; a phase control unit for detecting a phase difference between said phase reference signal and said output signal of said rotation detector and for outputting the detection results in numerical values; a speed reference signal generating unit having a register means for storing data specifying a pulse width of said speed reference signal; a speed control unit which uses said speed reference signal for detecting the cycle period of said output signal of said rotation detector and for outputting the detection results in numerical values; a full adder for adding the outputs of said phase control unit and said speed control unit and for outputting data corresponding to the computational results thereof; a direct register means for storing data in connection with a motor speed control signal; a selecting circuit for selecting either data stored from said direct register means or said data output from said full adder, and a signal converting unit for outputting the motor speed control signal corresponding to the content selected by said selecting circuit; wherein said phase control unit is provided with a register means for storing data specifying a detectable range of phase difference with respect to the whole variation width of an output value of said phase control unit; wherein said speed control unit includes a register means for storing data specifying a detectable range of a cycle period with respect to the whole variation width of the output value of said speed control unit; and wherein said controller further comprises a controller means for providing signals for setting said register means of said speed and phase control unit.

Claim 11

A servomotor controller as set forth in claim 8, wherein said phase control unit further comprising a circuit for thinning out a number of clock pulse which are determined by a thinning out part of said data from a predetermined number of clock pulses, a circuit means for frequency dividing a pulse train in an output from said thinning out circuit by a number determined by a dividing part of said data, and a counter for counting an output from said frequency dividing circuit, so that the value counted by said counter which is determined by a phase difference between said reference signal and said output signal of said rotation detector is used as an output of said phase control unit.

Claim 12

A servomotor controller as set forth in claim 8, wherein said speed control unit includes a circuit for thinning out a number of clock pulses determined by a thinning out part of said data from a predetermined number of clock pulses, a circuit means for frequency dividing a pulse train in an amount from said thinning out circuit by a number determined by a dividing part of said data, and a counter for counting an output of said frequency dividing circuit, so that the value counted by said counter which is determined by a pulse width of said speed reference signal and said output signal of said rotation detector is used as an output of said speed control unit.

Claim 13

A servomotor controller as set forth in claim 8, wherein said output of said speed control unit inverts the most significant bit thereof and inputs the inverted bit to said full adder.

Claim 14

A servomotor controller as set forth in claim 8, wherein said signal converting unit includes a pulse width modulating circuit which outputs a pulse signal of a duty ratio corresponding to the computation results of said full adder.

Claim 15

A servomotor controller as set forth in claim 12, including a logic circuit which causes said duty ratio of said pulse signal to be 1 or 0 when the computation result of said full adder is out of the predetermined range.

Claim 16

A servomotor controller as set forth in claim 8, wherein said signal converting unit includes a digital/analog converter for outputting a voltage signal corresponding to the computation result of said full adder.