US4500822A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital capstan servo circuit
Assignee: Sony Corp
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Filing: 1983-09-21
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Granted: 1985-02-19
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Expires: 2003-09-21
Abstract
Abstract A digital capstan servo circuit controls the rotation of a capstan motor used for sending a recording medium of a recording apparatus having a recording circuit for recording a plurality of pilot signals instead of CTL signals used for a tracking servo of the capstan motor in a reproducing mode. The pilot signals have different frequencies respectively and are recorded under being mixed with a video signal on video tracks. In the recording mode, a rotation speed information obtained from a counter of which a counting value is latched by a latch pulse produced from FG signals which are generated synchronously with the capstan motor and a rotation phase information obtained from the counter of which a counting value is latched by a latch pulse produced from an oscillator, an output signal of the oscillator having the same frequency as that of but a different phase from as that of the FG signals, are mixed to be a control signal of the capstan motor.
Inventors
- 👤 Shigeru Tajima
- 👤 Hiroshi Okada
- 👤 Kenji Nakano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:35
CPC Classifications
G; G11; G11B; G11B15/00; G11B15/18; G11B15/46; G11B15/467; G11B15/4673; G11B15/4675; G11B15/4676; G11B15/4677; G11B15/4678; H; H02; H02P; H02P23/00; H02P23/18; H02P23/186; H02P23/22; Y; Y10; Y10S; Y10S388/00; Y10S388/907; Y10S388/911; Y10S388/912
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
347 words
A digital servo circuit for controlling the rotational speed and phase of a rotating motor in a magnetic recording/reproducing apparatus to a desired speed and desired phase relative to a fixed phase by supplying a control signal to said motor, said digital servo circuit comprising: a source of FG pulse signals generated in synchronism with the rotation of said motor; means for generating a periodic pulse signal in response to each FG pulse signal, respectively, having the same period as said respective FG pulse signal and divided into first and second durations; a source of clock pulses having a predetermined frequency; means for cyclically counting said clock pulses during said second duration and producing a counted output in response thereto, said counted output being reset to zero after a cyclic period in which a maximum counted number of clock pulses have been counted; said frequency of said clock pulses and said maximum counted number being preselected such that, when said motor rotates at said preselected speed, the number of clock pulses occurring during said second duration exceeds said maximum counted number, whereby said second duration is divided into at least one complete cyclic period and a final incomplete period; first latch pulse generating means for producing a first latch pulse in response to said FG pulse signals during said first duration at a first timing position when said counted output is proportional to the rotational speed of the motor; first latch means for latching said counted output in response to said first latch pulse to produce a first counted value; second latch pulse generating means for producing a second latch pulse during said second duration at a second timing position when said counted output corresponds to the phase of said motor; second latch means for latching said counted output in response to said second latch pulse to produce a second counted value; means for generating said control signal in response to said first and second latched counted values, and means for supplying said control signal to said motor for controlling the phase and speed of said motor.
Claim 2
Dependent Claim
347 words
A digital servo circuit for controlling the rotational speed and phase of a rotating motor in a magnetic recording/reproducing apparatus to a desired speed and desired phase relative to a fixed phase by supplying a control signal to said motor, said digital servo circuit comprising: a source of FG pulse signals generated in synchronism with the rotation of said motor; means for generating a periodic pulse signal in response to each FG pulse signal, respectively, having the same period as said respective FG pulse signal and divided into first and second durations; a source of clock pulses having a predetermined frequency; means for cyclically counting said clock pulses during said second duration and producing a counted output in response thereto, said counted output being reset to zero after a cyclic period in which a maximum counted number of clock pulses have been counted; said frequency of said clock pulses and said maximum counted number being preselected such that, when said motor rotates at said preselected speed, the number of clock pulses occurring during said second duration exceeds said maximum counted number, whereby said second duration is divided into at least one complete cyclic period and a final incomplete period; first latch pulse generating means for producing a first latch pulse in response to said FG pulse signals during said first duration at a first timing position when said counted output is proportional to the rotational speed of the motor; first latch means for latching said counted output in response to said first latch pulse to produce a first counted value; second latch pulse generating means for producing a second latch pulse during said second duration at a second timing position when said counted output corresponds to the phase of said motor; second latch means for latching said counted output in response to said second latch pulse to produce a second counted value; means for generating said control signal in response to said first and second latched counted values, and means for supplying said control signal to said motor for controlling the phase and speed of said motor.
Claim 3
Dependent Claim
112 words
A digital servo circuit according to claim 1, wherein said phase of said motor is the phase difference between each FG pulse signal and the next occurring second latch pulse, and wherein a phase lock range is defined as a range of the phase of said motor about said desired phase, and a speed lock range is defined as a range of a rotational speed of said motor about said desired speed; and said second latch pulse occurs during a selected one of said at least one complete cyclic periods when said phase is within said phase lock range; and said first latch pulse occurs immediately after said final incomplete cyclic period.
Claim 4
Dependent Claim
120 words
A digital servo circuit according to claim 2, further comprising: means for detecting when the speed of said motor is out of said speed lock range in response to said counted output of said means for counting and for generating first and second latch override signals thereupon; means for supplying said first and second override signals to said first and second latch means, respectively, to control said first and second latch means independently of said first and second latch pulses, such that the output of said first latch means is in accordance with said counted output during said final incomplete period, and the output said second latch means is in accordance with said counted output during said selected complete period.
Claim 5
Dependent Claim
61 words
A digital servo circuit according to claim 1, wherein said means for generating said control signal includes: first and second digital to analog converters receiving the outputs of said first and second latch means, respectively, and for producing first and second analog outputs thereupon; and mixing means for generating said control signal in response to said first and second analog outputs.
Claim 6
Dependent Claim
31 words
A digital servo circuit according to claim 1, wherein said first and seocnd latch pulses are periodic signals with equal frequencies and are out of phase by a selected phase difference.
Claim 7
Dependent Claim
42 words
A digital servo circuit according to claim 2, further comprising: means for setting said second counted value to the counted output corresponding to one half said maximum counted number when said speed of said motor is outside of said speed lock range.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-02-19 | 1988-08-20 | 1989-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-02-19 | 1992-08-20 | 1993-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-02-19 | 1996-08-20 | 1997-02-19 | $7700.00 | Window Closed / Lapsed |