US5223733A
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US
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Semiconductor integrated circuit apparatus and method for designing the same
Assignee: Hitachi Ltd
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Filing: 1991-11-14
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Granted: 1993-06-29
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Expires: 2011-11-14
Abstract
Abstract A semiconductor integrated circuit device is provided which include a plurality of cell columns each having a number of unit cells previously fabricated on a semiconductor substrate selected from the plural kinds of unit cells which are formed in desired circuits by electrically connecting circuit devices previously arranged. Each column includes at least one kind of unit cell of a dynamic circuit which has a node in a floating state during the operation of the cell unit. A fixed potential shield layer is also provided on the cell columns so as to cover the nodes of the dynamic circuits. By virtue of this, a wiring area for electrically connecting the desired cell units can be located between the cell columns and above the shield layer. In other words, signal wirings in the wiring area can pass over the nodes of the dynamic circuits. without adverse parasitic effects. The unit cell can also be provided with a precharge circuit comprising a standard cell and an in-cell wiring layer. Further, clock input terminals of the unit cells which are provided with a precharge circuit can be divided into plural groups, with all of said clock input terminals belonging to the same group and having equal load capacitances being connected. Clock buffer cells can be provided for supplying clock signals to the clock signal wirings for each group.
Inventors
- 👤 Toshio Doi
- 👤 Takehisa Hayashi
- 👤 Kenichi Ishibashi
- 👤 Mitsuo Asai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:49
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/423; H10D; H10D89/00; H10D89/10
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
171 words
A semiconductor integrated circuit device comprising: a plurality of cell rows each including a plurality of unit cells which are formed by electrically connecting circuit components, each cell row comprising a least one kind of unit cell including a clock-controlled dynamic circuit which has a high-impedance node which is precharged under the control of an applied clock pulse to be in a floating state in operation of the cell unit; at least one shield layer, having a fixed potential, provided over said cell rows so as to cover the high-impedance nodes of the dynamic circuits of said unit cells, and a wiring area including at least a first signal wiring for electrically connecting desired ones of said unit cells, wherein said first signal wiring carries a signal having changes in potential level, said wiring area being located transversely above said shield layer so that said first signal wiring in said wiring area can extend over said nodes of said dynamic circuits without effecting the floating state of the dynamic circuit node.
Claim 2
Dependent Claim
171 words
A semiconductor integrated circuit device comprising: a plurality of cell rows each including a plurality of unit cells which are formed by electrically connecting circuit components, each cell row comprising a least one kind of unit cell including a clock-controlled dynamic circuit which has a high-impedance node which is precharged under the control of an applied clock pulse to be in a floating state in operation of the cell unit; at least one shield layer, having a fixed potential, provided over said cell rows so as to cover the high-impedance nodes of the dynamic circuits of said unit cells, and a wiring area including at least a first signal wiring for electrically connecting desired ones of said unit cells, wherein said first signal wiring carries a signal having changes in potential level, said wiring area being located transversely above said shield layer so that said first signal wiring in said wiring area can extend over said nodes of said dynamic circuits without effecting the floating state of the dynamic circuit node.
Claim 3
Dependent Claim
56 words
A semiconductor integrated circuit device according to claim 1, wherein said at least one kind of unit cell including a dynamic circuit comprises a standard cell in which circuit components are previously arranged in accordance with a predetermined layout and which includes an in-cell wiring layer for electrically connecting the circuit components of the standard cell.
Claim 4
Dependent Claim
45 words
A semiconductor integrated circuit device according to claim 1, wherein said shield layer is located along each cell row so as to cover the cell row, and serves as a power supply wiring layer for supplying power to the unit cells in each cell row.
Claim 5
Dependent Claim
43 words
A semiconductor integrated circuit device according to claim 3, wherein said power supply wiring layer comprises a first wiring fixed at a predetermined potential other than ground and a ground wiring, wherein said first wiring and said ground wiring are arranged in parallel.
Claim 6
Dependent Claim
24 words
A semiconductor integrated circuit device according to claim 1, wherein each unit cell comprises at least one MOSFET and at least one bipolar transistor.
Claim 7
Dependent Claim
71 words
A semiconductor integrated circuit device according to claim 1, comprising at least four layers for wiring arranged on said semiconductor substrate, the first and second layers from the bottom of said four layers being used as wiring layers for connecting the circuit components in the unit cells, the third layer being used as said shield layer, and the fourth layer being used as a wiring layer for connecting the unit cells.
Claim 8
Dependent Claim
34 words
A semiconductor integrated circuit device according to claim 6, wherein each unit cell comprises at least one MOSFET transistor, wherein gates of MOSFET's in each unit cell are connected using said first wiring layer.
Claim 9
Dependent Claim
24 words
A semiconductor integrated circuit device according to claim 1, wherein one of said plural kinds of unit cells is formed of a static circuit.
Claim 10
Dependent Claim
38 words
A semiconductor integrated circuit device according to claim 1, further comprising a clock signal wiring formed between said cell rows, said clock signal wiring being connected with clock input terminals in unit cells formed of said dynamic circuits.
Claim 11
Dependent Claim
27 words
A semiconductor integrated circuit device according to claim 9, wherein said clock signal wiring has a width larger than that first signal wirings in said wirings area.
Claim 12
Dependent Claim
34 words
A semiconductor integrated circuit device according to claim 9, wherein said clock signal wiring is located at a position nearer to each of said cell rows than other wirings located between said cell rows.
Claim 13
Dependent Claim
43 words
A semiconductor integrated circuit device according to claim 1, wherein said plural kinds of unit cells comprise plural unit cells having the same logic capability as one anther but different in at least one characteristic of propagation delay, circuit form and constituent components.
Claim 14
Dependent Claim
29 words
A semiconductor integrated circuit device according to claim 1, wherein said plural kinds of unit cells comprise unit cells including bipolar transistors and unit cells not including bipolar transistors.
Claim 15
Dependent Claim
92 words
A semiconductor integrated circuit device according to claim 2, further comprising contact-holes located at a first group of predetermined positions in accordance with a predetermined lattice pattern for electrically connecting the in-cell wiring layer with said circuit components, and through-holes located at a second group of predetermined positions in accordance with said predetermined lattice pattern for electrically connecting the in-cell wiring layer with a power supply wiring layer, wherein an in-cell wiring on said in-cell wiring layer for electrically connecting said circuit components is located in accordance with said predetermined lattice pattern.
Claim 16
Dependent Claim
25 words
A semiconductor integrated circuit device according to claim 2, wherein said standard cell includes either or both of an MOSFET area and bipolar transistor area.
Claim 17
Dependent Claim
71 words
A semiconductor integrated circuit device according to claim 2, wherein said standard cell includes a first group of MOSFETs of a first conductivity type and a second group of MOSFETs of an opposite conductivity type, wherein at least the first group of MOSFETs has a first subgroup of MOSFETs having a first gate width and a second subgroup of MOSFETs having a second gate width different than the first gate width.
Claim 18
Dependent Claim
46 words
A semiconductor integrated circuit device according to claim 1, wherein said unit cell provided with a dynamic circuit comprises a standard cell in which circuit components are previously arranged in accordance with a predetermined layout and an in-cell wiring layer for electrically connecting the circuit components.
Claim 19
Dependent Claim
40 words
A semiconductor integrated circuit device according to claim 1, wherein said unit cells include at least one kind of clock buffer cell for producing clock signals to be supplied to the unit cells which are provided with a dynamic circuit.
Claim 20
Dependent Claim
76 words
A semiconductor integrated circuit device according to claim 1, wherein unit cells provided with a dynamic circuit include clock input terminals which are divided into plural groups, said device further comprising clock signal wirings connected with all said clock input terminals belonging to one of said plural groups wherein said clock signal wirings all have substantially the same load capacitance, and clock buffer cells for supplying clock signals to said clock signal wirings for each group.
Claim 21
Dependent Claim
26 words
A semiconductor integrated circuit device according to claim 19, wherein said clock buffer cells are provided one by one for each group in said cell rows.
Claim 22
Dependent Claim
217 words
A semiconductor integrated circuit device in a standard cell system including a plurality of unit cells which are formed by electrically connecting circuit components, comprising: at least one kind of unit cell including a clock-controlled dynamic circuit which has a high-impedance node which is precharged under the control of an applied clock pulse to be in a floating state in operation of the cell unit, said unit cell being included in the plurality of unit cells, at least one wiring layer for connecting said circuit components in each of the unit cells arranged on the substrate, at least one shield layer, having a fixed potential, provided so as to cover at least the high-impedance node of the dynamic circuit, and at least one signal wiring layer located transversely above the shield layer to extend over the node of the dynamic circuit, wherein said signal wiring layer includes at least a first signal wiring for electrically connecting desired ones of the unit cells wherein the first signal wiring carries a signal having changes in potential level and wherein said shield layer is located between the node of the dynamic circuit and the first signal wiring to prevent changes in the potential level on the first signal wiring from adversely affecting the floating state of the dynamic circuit node.
Claim 23
Dependent Claim
217 words
A semiconductor integrated circuit device in a standard cell system including a plurality of unit cells which are formed by electrically connecting circuit components, comprising: at least one kind of unit cell including a clock-controlled dynamic circuit which has a high-impedance node which is precharged under the control of an applied clock pulse to be in a floating state in operation of the cell unit, said unit cell being included in the plurality of unit cells, at least one wiring layer for connecting said circuit components in each of the unit cells arranged on the substrate, at least one shield layer, having a fixed potential, provided so as to cover at least the high-impedance node of the dynamic circuit, and at least one signal wiring layer located transversely above the shield layer to extend over the node of the dynamic circuit, wherein said signal wiring layer includes at least a first signal wiring for electrically connecting desired ones of the unit cells wherein the first signal wiring carries a signal having changes in potential level and wherein said shield layer is located between the node of the dynamic circuit and the first signal wiring to prevent changes in the potential level on the first signal wiring from adversely affecting the floating state of the dynamic circuit node.
Claim 24
Dependent Claim
24 words
A semiconductor integrated circuit device according to claim 21, wherein said shield layer is comprised of a power supply wiring and a ground wiring.
Claim 25
Dependent Claim
72 words
A semiconductor integrated circuit device according to claim 22, comprising at least four layers for wiring arranged on said semiconductor substrate, the first and second layers from bottom of said four layers of wiring being used as wiring layers for connecting the circuit components in the unit cells, the third layer being used as said shield layer, and the fourth layer being used as a wiring layer for connecting the unit cells.
Claim 26
Dependent Claim
44 words
A semiconductor integrated circuit device according to claim 23, wherein each unit cell comprises at least one MOSFET transistor, and wherein said first wiring layer is used to form a gate electrode of the at least one MOSFET in each of said unit cells.
Claim 27
Dependent Claim
22 words
A circuit device according to claim 1, wherein said wiring area is located transversely to at least one of said cell rows.
Claim 28
Dependent Claim
23 words
A circuit device according to claim 1, wherein said wiring area is located vertically transversely to at least one if said cell rows.
Claim 29
Dependent Claim
278 words
A semiconductor integrated circuit device comprising: a plurality of cell rows each including a plurality of unit cells previously fabricated on a semiconductor substrate selected from plural kinds of unit cells which are formed by electrically connecting circuit components; a clock signal wiring for supplying a clock signal to said cell rows; at least one shield layer having a fixed potential and provided over predetermined portions of said cell rows; and a wiring area including at least a first signal wiring for electrically connecting predetermined ones of said unit cells, wherein each of said cell rows comprises at least one kind of unit cell including a clock-controlled dynamic circuit which has a high-impedance node in a floating state to be precharged in response to the supplied clock signal in operation of the unit cell, and wherein said at least one shield layer having the fixed potential is provide dover the predetermined portions of said cells rows so as to cover the high-impedance nodes of the dynamic circuits of said predetermined ones of said unit cells, and said first signal wiring carries a signal having changes in potential level, said wiring area being located transversely above said shield layer for the electrical connection of the predetermined unit cells, so that said first signal wiring in said wiring area can extend over said nodes of said dynamic circuits of the predetermined unit cells without changes in the potential level on the first signal wiring adversely affecting the floating state of the dynamic circuit nodes, whereby said wiring area and said first signal wiring can be freely located without being restricted by location of said high-impedance nodes of said dynamic circuits.
Claim 30
Dependent Claim
278 words
A semiconductor integrated circuit device comprising: a plurality of cell rows each including a plurality of unit cells previously fabricated on a semiconductor substrate selected from plural kinds of unit cells which are formed by electrically connecting circuit components; a clock signal wiring for supplying a clock signal to said cell rows; at least one shield layer having a fixed potential and provided over predetermined portions of said cell rows; and a wiring area including at least a first signal wiring for electrically connecting predetermined ones of said unit cells, wherein each of said cell rows comprises at least one kind of unit cell including a clock-controlled dynamic circuit which has a high-impedance node in a floating state to be precharged in response to the supplied clock signal in operation of the unit cell, and wherein said at least one shield layer having the fixed potential is provide dover the predetermined portions of said cells rows so as to cover the high-impedance nodes of the dynamic circuits of said predetermined ones of said unit cells, and said first signal wiring carries a signal having changes in potential level, said wiring area being located transversely above said shield layer for the electrical connection of the predetermined unit cells, so that said first signal wiring in said wiring area can extend over said nodes of said dynamic circuits of the predetermined unit cells without changes in the potential level on the first signal wiring adversely affecting the floating state of the dynamic circuit nodes, whereby said wiring area and said first signal wiring can be freely located without being restricted by location of said high-impedance nodes of said dynamic circuits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-28 | 1996-12-28 | 1997-06-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-28 | 2000-12-28 | 2001-06-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-28 | 2004-12-28 | 2005-06-29 | $7700.00 | Window Closed / Lapsed |