Method for producing a layered capacitor structure for a dynamic random access memory device

Claim 1

A method for producing a layer structure of a memory cell of a dynamic random access memory device comprising: forming on a semiconductor body a first insulation film on the surface, and a transfer FET including source and drain regions; forming a first polysilicon layer over the surface of said semiconductor body; forming an opening in said first polysilicon layer over said drain region; depositing a doped second polysilicon layer over said first polysilicon layer; forming a second insulating layer over said second polysilicon layer; exposing the semiconductor body to reactive ion etching to remove said second insulation layer from all horizontal surface, including over said drain region, but leaving portions thereof on the adjacent vertical and steeply inclined surfaces; removing the portions of the exposed second polysilicon layer at least over said drain region; removing the resultant exposed first insulation film over said drain region, and the remaining portions of said second insulation layer by chemical etching; depositing a third polysilicon layer on said semiconductor body; ion implanting a dopant into said third polysilicon layer; and removing portion of said first and third polysilicon layers over said semiconductor body, but leaving the portions about and in contact with said drain regions which constitutes a capacitor for said memory cell.

Claim 2

A method for producing a layer structure of a memory cell of a dynamic random access memory device comprising: forming on a semiconductor body a first insulation film on the surface, and a transfer FET including source and drain regions; forming a first polysilicon layer over the surface of said semiconductor body; forming an opening in said first polysilicon layer over said drain region; depositing a doped second polysilicon layer over said first polysilicon layer; forming a second insulating layer over said second polysilicon layer; exposing the semiconductor body to reactive ion etching to remove said second insulation layer from all horizontal surface, including over said drain region, but leaving portions thereof on the adjacent vertical and steeply inclined surfaces; removing the portions of the exposed second polysilicon layer at least over said drain region; removing the resultant exposed first insulation film over said drain region, and the remaining portions of said second insulation layer by chemical etching; depositing a third polysilicon layer on said semiconductor body; ion implanting a dopant into said third polysilicon layer; and removing portion of said first and third polysilicon layers over said semiconductor body, but leaving the portions about and in contact with said drain regions which constitutes a capacitor for said memory cell.