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US5222230A
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Circuitry for transferring data from a data bus and temporary register into a plurality of input registers on clock edges
Assignee: Texas Instruments Inc
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Filing: 1989-11-20
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Granted: 1993-06-22
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Expires: 2009-11-20
Abstract
Abstract A floating point processor (10) is provided having a multiplier (48) and an ALU (54) for performing arithmetic calculations simultaneously. The output of the multiplier (48) and ALU (54) are stored in a product register (64) and a sum register (66), respectively. Multiplexers (40,42,44,46) are provided at the inputs to the multiplier (48) and the ALU (54). The multiplexers choose between data in input registers (32,34), product and sum registers (64,66), and an output register (76). Since the multiplier (48) and ALU (54) operate simultaneously, and since the outputs of the multiplier (48) and ALU (54) are available to the multiplexers (40-46), product of sums calculations and sum of products calculations may be performed rapidly. An input stage (12) uses a temporary register (18) to store data from a data bus on the first clock edge, and configuration logic (28) for directing data from the data bus and the temporary register (18) to the input registers (32,34) on a second clock edge.
Inventors
- 👤 Michael C. Gill
- 👤 Henry M. Darley
- 👤 Edison H. Chiu
- 👤 Jeffrey A. Niehaus
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:16
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/483; G06F7/544; G06F7/5443
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
56 words
A method of receiving data from a data bus comprising the steps of: receiving data from the data bus into a temporary register on a first clock edge responsive to a configuration signal; and selectively transferring data from said temporary register and the data bus into a plurality of input registers on a second clock edge.
Claim 2
Independent Claim
56 words
A method of receiving data from a data bus comprising the steps of: receiving data from the data bus into a temporary register on a first clock edge responsive to a configuration signal; and selectively transferring data from said temporary register and the data bus into a plurality of input registers on a second clock edge.
Claim 3
Dependent Claim
67 words
The method of claim 1, wherein said step of storing data in said temporary register comprises the step of storing data in said temporary register from the data bus upon a falling edge of a clock pulse and said step of transferring data comprises transferring data from said temporary register and the data bus to said input registers upon the next rising edge of said clock pulse.
Claim 4
Dependent Claim
67 words
The method of claim 1 wherein said step of storing data in said temporary register comprises the step of storing data in said temporary register from the data bus upon a rising edge of a clock pulse and said step of transferring data comprises transferring data from said temporary register and the data bus to said input registers upon the next falling edge of said clock pulse.
Claim 5
Dependent Claim
106 words
Circuitry for receiving data from a bus comprising: a temporary register for storing data present on said data bus at a first clock edge; a first input register for storing a data word comprising bits from said data bus; a second input register for storing a data word comprising bits from said data bus; and configuration logic connected between said temporary register and said first and second input registers and between the data bus and said first and second input data registers for selectively connecting portions of the data bus and said temporary register to said first and second input registers at a second clock edge.
Claim 6
Dependent Claim
106 words
Circuitry for receiving data from a bus comprising: a temporary register for storing data present on said data bus at a first clock edge; a first input register for storing a data word comprising bits from said data bus; a second input register for storing a data word comprising bits from said data bus; and configuration logic connected between said temporary register and said first and second input registers and between the data bus and said first and second input data registers for selectively connecting portions of the data bus and said temporary register to said first and second input registers at a second clock edge.
Claim 7
Dependent Claim
55 words
The integrated circuit of claim 4 wherein: said temporary register is operable to latch data on a following edge of a clock pulse; and said configuration logic circuitry is operable to connect said temporary register and the data bus to said first and second input registers upon the next rising edge of said clock pulse.
Claim 8
Dependent Claim
55 words
The integrated circuit of claim 4 wherein: said temporary register is operable to latch data on a rising edge of a clock pulse; and said configuration logic circuitry is operable to connect said temporary register and the data bus to said first and second input registers upon the next falling edge of said clock pulse.
Claim 9
Dependent Claim
229 words
The circuitry of claim 4 wherein said configuration logic comprises: circuitry to selectively connect the high order bits of said temporary register to either the high order bits of said first input register, the high order bits of said second input register, or the low order bits of said second input register responsive to a control signal; circuitry to selectively connect the low order bits of the data in said temporary register to either the high order bits of said first input register, the low order bits of said first input register, the high order bits of said second input register, or the low order bits of said second input register responsive to said control signal; circuitry to selectively connect the high order bits from the data bus to either the high order bits of said first input register, the low order bits of said first input register, the high order bits of said second input register, or the low order bits of said second input register responsive to said control signal; and circuitry to selectively connect the low order bits from the data bus to either the high order bits of said first input register, the low order bits of said first input register, the high order bits of said second input register, or the low order bits of said second input register responsive to said control signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-21 | 1996-12-21 | 1997-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-21 | 2000-12-21 | 2001-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-21 | 2004-12-21 | 2005-06-22 | $7700.00 | Window Closed / Lapsed |