Circuit and method for cancelling nonlinearity error associated with component value mismatches in a data converter

Claim 2

A circuit for cancelling nonlinearity error associated with component value mismatches in a data converter having a plurality of components which are each selectively switched between first and second terminals to perform a predetermined data conversion, comprising: arithmetic circuitry for successively receiving a plurality of digital input signals, the arithmetic circuitry successively performing a predetermined arithmetic operation for each digital input signal and using an immediately preceding output of the arithmetic circuitry to provide an output for each received input signal, a first output being provided by using a first of the digital input signals and a predetermined value; an encoder coupled to the arithmetic circuitry for receiving the output provided in response to each received digital input signal, the encoder translating the output from a first predetermined digital code value to a second predetermined digital code value; and control signal circuitry coupled to the arithmetic circuitry and the encoder, the control signal circuitry providing a plurality of control signals for controlling switching of the plurality of components in a predetermined order to cancel the nonlinearity error by switching a predetermined number of the components for each received digital input signal as determined by the second predetermined digital code value and in a non-repetitive successive order with respect to successive digital input signals, the successive order to switching of components being repeated for subsequent digital input signals after one or more of the digital input signals has generated enough control signals to cause each of the components to be switched once.

Claim 3

The circuit of claim 1 wherein the arithmetic circuitry is an N-bit adder, where N is an integer, and each of the plurality of digital input signals is an N-bit signal, the N-bit adder summing a carry out bit, when a carry out bit is generated in connection with providing the initial sum, wherein the summing of the carry out bit with the initial sum provides the final sum.

Claim 4

The circuit of claim 1 wherein the control signal circuitry comprises: a plurality of logic gates which uses: (1) the second predetermined digital code value of an immediately preceding digital input signal except for initially using a reset value; (2) the second predetermined digital code value of a digital input signal being presently processed; and (3) the carry-out bit to provided each of the plurality of control signals.

Claim 5

The circuit of claim 3 wherein the plurality of logic gates comprise a plurality of groups of logic gates, each group comprising: a first exclusive NOR gate having a first input coupled to the encoder for receiving a predetermined bit of the second predetermined digital code value of the digital input signal being presently processed, a second input coupled to the encoder for receiving a predetermined bit of the second predetermined digital code value of the immediately preceding digital input signal, and an output; and a second exclusive NOR gate having a first input coupled to the output of the first exclusive NOR gate, a second input coupled to an inverse of the carry-out bit, and an output for providing one of the control signals.

Claim 6

The circuit of claim 3 wherein the control signal circuitry further comprises: a latch having an input coupled to the encoder and an output coupled to the plurality of logic gates, the latch providing the second predetermined digital code value of the immediately preceding digital input signal.

Claim 7

The circuit of claim 5 wherein the arithmetic circuitry is initially reset with a first predetermined initial value as the predetermined value, and the latch is initially reset with a second predetermined initial value as a first output of the latch.

Claim 8

The circuit of claim 1 wherein the first predetermined digital code value is a binary code value, and the second predetermined digital code value is a thermometer code value.

Claim 9

In a data converter having a plurality of components which are each selectively switched between first and second terminals to perform a predetermined data conversion, a method for cancelling nonlinearity error associated with component value mismatches, comprising the steps of: successively receiving a plurality of digital input signals; successively performing a predetermined arithmetic operation with each digital input signal and an immediately preceding output of the predetermined arithmetic operation to provide an output for each received input signal, a first arithmetic operation using a predetermined value and a first digital input signal; translating the output for each received digital input signal from a first predetermined digital code to a second predetermined digital code value; providing a plurality of control signals for controlling switching of the plurality of components in a predetermined order to cancel the nonlinearity error by switching a predetermined number of the components for each received digital input signal as determined by the second predetermined digital code value and in a non-repetitive successive order with respect to successive digital input signals; and repeating the successive order of switching of components in response to subsequent digital input signals after the plurality of control signals from one or more of the digital input signals has caused each of the components to be switched once.

Claim 10

In a data converter having a plurality of components which are each selectively switched between first and second terminals to perform a predetermined data conversion, a method for cancelling nonlinearity error associated with component value mismatches, comprising the steps of: successively receiving a plurality of digital input signals; successively performing a predetermined arithmetic operation with each digital input signal and an immediately preceding output of the predetermined arithmetic operation to provide an output for each received input signal, a first arithmetic operation using a predetermined value and a first digital input signal; translating the output for each received digital input signal from a first predetermined digital code to a second predetermined digital code value; providing a plurality of control signals for controlling switching of the plurality of components in a predetermined order to cancel the nonlinearity error by switching a predetermined number of the components for each received digital input signal as determined by the second predetermined digital code value and in a non-repetitive successive order with respect to successive digital input signals; and repeating the successive order of switching of components in response to subsequent digital input signals after the plurality of control signals from one or more of the digital input signals has caused each of the components to be switched once.

Claim 11

The method for cancelling nonlinearity error of claim 8 wherein the step of successively receiving a plurality of digital input signals comprises receiving a plurality of digital input signals, each having N bits, where N is an integer, and the step of providing a plurality of control signals comprises providing a plurality of control signals, each plurality having (2 N -1) control signals.

Claim 12

The method for cancelling nonlinearity error of claim 8 wherein the step of translating further comprises translating from a binary code to a thermometer code.

Claim 13

An error correction circuit for cancelling nonlinearity error associated with component value mismatches in a digital-to-analog (D/A) converter having a plurality of components which are each selectively switched between first and second terminals to perform a predetermined data conversion, comprising: adder means for successively receiving a plurality of digital input signals, the adder means successively adding each digital input signal with a previously existing sum generated from an immediately preceding digital input signal to provide an initial sum for each received input signal, a first of the digital input signals being summed with a predetermined value, the adder means also selectively adding a carry-out bit to a least significant bit position of the initial sum to provide a final sum for each received digital input signal; encoding means coupled to the adder means for receiving the final sum provided in response to each received digital input signal, the encoding means translating the final sum from a first predetermined digital code value to a second predetermined digital code value; and output means coupled to the adder means and the encoding means, the output means providing a plurality of control signals for controlling switching of the plurality of components in a predetermined order to cancel the nonlinearity error by switching a predetermined number of the components for each received digital input signal as determined by the second predetermined digital code value and in a non-repetitive successive order with respect to successive digital input signals, the successive order of switching of components being repeated for subsequent digital input signals after one or more of the digital input signals has generated enough control signals to cause each of the components to be switched once.

Claim 14

An error correction circuit for cancelling nonlinearity error associated with component value mismatches in a digital-to-analog (D/A) converter having a plurality of components which are each selectively switched between first and second terminals to perform a predetermined data conversion, comprising: adder means for successively receiving a plurality of digital input signals, the adder means successively adding each digital input signal with a previously existing sum generated from an immediately preceding digital input signal to provide an initial sum for each received input signal, a first of the digital input signals being summed with a predetermined value, the adder means also selectively adding a carry-out bit to a least significant bit position of the initial sum to provide a final sum for each received digital input signal; encoding means coupled to the adder means for receiving the final sum provided in response to each received digital input signal, the encoding means translating the final sum from a first predetermined digital code value to a second predetermined digital code value; and output means coupled to the adder means and the encoding means, the output means providing a plurality of control signals for controlling switching of the plurality of components in a predetermined order to cancel the nonlinearity error by switching a predetermined number of the components for each received digital input signal as determined by the second predetermined digital code value and in a non-repetitive successive order with respect to successive digital input signals, the successive order of switching of components being repeated for subsequent digital input signals after one or more of the digital input signals has generated enough control signals to cause each of the components to be switched once.

Claim 15

The error correction circuit of claim 11 wherein the output means comprise: a plurality of logic gates which uses the second predetermined digital code value of an immediately preceding digital input signal except for initially using a reset value, the second predetermined digital code value of a digital input signal being presently processed, and the carry-out bit to provide each of the plurality of control signals.

Claim 16

The error correction circuit of claim 12 wherein the plurality of logic gates comprise a plurality of groups of logic gates, each group comprising: a first exclusive NOR gate having a first input coupled to the encoder for receiving the second predetermined digital code value of the digital input signal being presently processed, a second input coupled to the encoder for receiving the second predetermined digital code value of the immediately preceding digital input signal, and an output; and a second exclusive NOR gate having a first input coupled to the output of the first exclusive NOR gate, a second input coupled to an inverse of the carry-out bit, and an output for providing one of the control signals.

Claim 17

The error correction circuit of claim 11 wherein the encoding means translates the final sum from a binary code value to a thermometer code value.