US4894656A
Expired / Lapsed
US
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Self-calibrating pipelined subranging analog-to-digital converter
Assignee: CARDINAL SCALE MANUFACTURING COMPANY A CORP OF
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Filing: 1988-11-25
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Granted: 1990-01-16
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Expires: 2008-11-25
Abstract
Abstract An approach to A/D converter architecture is based on a "pipelined and submerged" architecture which includes a pipeline of elemental stages (10 i ). Each stage of the pipeline comprises a low-resolution flash A/D subconverter (12), a D/A converter (14), and a unity-gain buffer (16). To minimize converter nonlinearity due to component mismatches, a self calibration technique based on an "interpolation" scheme is used. This technique employs an on-chip delta-sigma A/D converter (32) to provide the reference for calibration and a 100-bit memory (50) to store nonlinearity information. Long term drift is corrected by a calibrator (34) in parallel with data conversion.
Inventors
- 👤 Jyh-Ping Hwang
- 👤 Wen-Tai Lin
- 👤 Miran Milkovic
- 👤 Sharbel E. Noujaim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:31
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/10; H03M1/1009; H03M1/1033; H03M1/1038; H03M1/12; H03M1/34; H03M1/38; H03M1/44
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
133 words
A self-calibrating pipelined subranging analog-to-digital converter comprising: sample-and-hold means for sampling an analog signal to be converted to a digital output, a pipeline of elemental stages connected for sampling said analog signal to generate a low-resolution output digital code; calibration means including memory and arithmetic means addressed by said low-resolution output digital code for storing nonlinearity information and computing a second output digital code based on an interpolation of said low-resolution output digital code with said nonlinearity information; and a high-resolution analog-to-digital converter connected to said sample-and-hold means and responsive to samples of said analog signal to generate a high-resolution output digital code, said high resolution output digital code serving as a reference, said calibration means being periodically responsive to said high resolution output digital code for calibrating said memory and arithmetic means.
Claim 2
Dependent Claim
133 words
A self-calibrating pipelined subranging analog-to-digital converter comprising: sample-and-hold means for sampling an analog signal to be converted to a digital output, a pipeline of elemental stages connected for sampling said analog signal to generate a low-resolution output digital code; calibration means including memory and arithmetic means addressed by said low-resolution output digital code for storing nonlinearity information and computing a second output digital code based on an interpolation of said low-resolution output digital code with said nonlinearity information; and a high-resolution analog-to-digital converter connected to said sample-and-hold means and responsive to samples of said analog signal to generate a high-resolution output digital code, said high resolution output digital code serving as a reference, said calibration means being periodically responsive to said high resolution output digital code for calibrating said memory and arithmetic means.
Claim 3
Dependent Claim
18 words
The self-calibrating pipelined subranging analog-to-digital converter of claim 1 wherein said high-resolution analog-to-digital converter comprises a delta-sigma converter.
Claim 4
Dependent Claim
64 words
The self-calibrating pipelined subranging analog-to-digital converter of claim 1 wherein each respective stage of said pipeline comprises: a low-resolution flash analog-to-digital subconverter generating a portion of said low-resolution output digital code; digital-to-analog converter means responsive to said analog-to-digital subconverter for producing a subrange output voltage for the stage; and buffer means for supplying said subrange output voltage to a successive stage of the pipeline.
Claim 5
Dependent Claim
29 words
The self-calibrating pipelined subranging analog-to-digital converter of claim 3 wherein said digital-to-analog converter means comprises a switch network means controlled by said portion of said low-resolution output digital code.
Claim 6
Dependent Claim
16 words
The self-calibrating pipelined subranging analog-to-digital converter of claim 4 wherein said buffer means exhibits unity gain.
Claim 7
Dependent Claim
80 words
The self-calibrating pipelined subranging analog-to-digital converter recited in claim 5 wherein said switch network means includes a resistive network and a plurality of switches, each of said switches, respectively, being connected to a junction, respectively, in said resistive network for selectively connecting a first one of the junctions to said unity-gain buffer means and a second one of said junctions to said unity-gain buffer means, such that a voltage drop between said first and second junctions constitutes said subrange voltage.
Claim 8
Dependent Claim
74 words
The self-calibrating pipelined subranging analog-to-digital converter of claim 6 wherein said flash analog-to-digital subconverter comprises decoder and encoder means for controlling the positions of said switches, and a plurality of comparator means for providing input signals to said decoder and encoder means, each of said comparator means having a first input responsive to said samples of said analog signal, and a second input respectively connected to an additional junction, respectively, in said resistive network.
Claim 9
Dependent Claim
68 words
The self-calibrating pipelined subranging analog-to-digital converter of claim 1 wherein each respective stage of said pipeline comprises: a low-resolution successive-approximation analog-to-digital subconverter generating a portion of said low-resolution output digital code; means controlled by said portion of said low resolution output digital code for producing a subrange output voltage for the stage; and buffer means for supplying said subrange output voltage to a successive stage of the pipeline.
Claim 10
Dependent Claim
67 words
The self-calibrating pipelined subranging analog-to-digital converter of claim 1 wherein each respective stage of said pipeline comprises: a low-resolution oversampled delta-sigma analog-to-digital subconverter generating a portion of said low-resolution output digital code; means controlled by said portion of said low-resolution output digital code for producing a subrange output voltage for the stage; and buffer means connecting said subrange voltage output to a successive stage of the pipeline.
Claim 11
Dependent Claim
156 words
The self-calibrating pipelined subranging analog-to-digital converter of claim 1 wherein said calibration means further comprises: first and second counter means, said first counter means counting a first n 1 -bit number x and said second counter means counting a second s-bit number y; comparator means for comparing said low-resolution output digital code with said number x and when the most significant n 1 bits of said low-resolution output digital code are equal to an output count of said first counter, producing said low-resolution output digital code; and computation means responsive to said second counter means for repetitively subtracting said highresolution output digital code from the low-resolution output digital code of said comparator means and accumulating a difference output and, when said number y reaches 2 s , dividing the accumulated difference by 2 s to produce an averaged linearity error, said averaged linearity error being stored in said memory and arithmetic means as said nonlinearity information.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-15 | 1993-07-17 | 1994-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-15 | 1997-07-17 | 1998-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-15 | 2001-07-17 | 2002-01-16 | $7700.00 | Window Closed / Lapsed |