Multiple channel analog-to-digital converter with automatic calibration

Claim 2

A multiple channel analog-to-digital converter comprising: a. a ramp generator for generating a ramp signal; b. a digital counter for generating a count output indicative of the instantaneous count within said counter; c. a control means responsive to said ramp signal and to the count within said digital counter and operative to maintain the time coincidence of a zero count in said counter and a first value of said ramp signal, and a full scale count in said counter and a second value of said ramp signal, wherein said control means comprises; i. a first means responsive to said ramp signal and operative to generate an analog full scale signal whenever said ramp signal equals said second value, ii. a second means responsive to the count in said counter and operative to generate a digital full scale signal whenever said counter reaches said full scale count, and iii. a third means responsive to said analog full scale signal and said digital full scale signal and operative to vary the slope of said ramp signal in accordance with the difference between the time occurrence of said analog full scale signal and said digital full scale signal, iv. a fourth means responsive to said ramp signal and operative to reset said counter to a zero count upon the occurrence of said first value; d. means comprising at least one channel, each channel comprising; i. a compare means responsive to an analog input signal and operative to generate a compare signal whenever said analog input is equal to said ramp output; and ii. a buffer means responsive to said compare signal and operative to transfer the count of said counter to said buffer for effectively producing in said buffers the digital value associated with the analog value of the analog input signal to said compare means.

Claim 3

A multi-channel analog-to-digital converter as recited in claim 1 wherein said control means comprises a fifth means responsive to the count in said counter and to said digital full scale signal and operative to control the sign of said ramp signal.

Claim 4

A multi-channel analog-to-digital converter as recited in claim 2 further comprising a sixth means responsive to said digital full scale signal and operative to block said compare signals upon the occurrence of said full scale count in said counter during each cycle of operation of the multi-channel analog-to-digital converter.

Claim 5

A multiple channel analog-to-digital converter comprising: a. an analog input signal; b. a ramp generator for generating a ramp signal; c. a digital counter for generating a count output indicative of the instantaneous count within said counter; d. a first detecting means responsive to said ramp signal and operative to generate a first output signal whenever said ramp output signal is equal to a reference voltage; e. a timing means responsive to said first output signal and to a full scale count in said counter and operative to reset said ramp generator upon the occurrence of said full scale count, and reset and start said counter upon the occurrence of said first output signal, wherein said timing means comprises; i. a second detector responsive to such full scale count and operative to generate a second output signal for resetting said ramp generator upon the occurrence of said full scale count; and ii. means responsive to said second and first output signals and operative to reset said counter and said second detector upon the occurrence of said second output signal and start said counter upon the occurrence of said first output signal; f. a compare means responsive to said analog input signal and operative to generate a compare signal when said analog input signal is equal to said ramp signal; and g. a buffer means responsive to said compare signal and operative to transfer the count of said counter to said buffer so as to effectively produce in said buffer the digital value associated with the value of said analog input signal, wherein each channel in the multiple channel analog-to-digital converter further comprises a blocking means responsive to the output of said timing means for preventing a compare signal from transferring the count in said counter to said buffer during the period of time between the occurrence of said second output signal and said first output signal.

Claim 6

A multiple channel analog-to-digital converter comprising: a. an analog input signal; b. a ramp generator for generating a ramp signal; c. a digital counter for generating a count output indicative of the instantaneous count within said counter; d. a first detecting means responsive to said ramp signal and operative to generate a first output signal whenever said ramp output signal is equal to a reference voltage; e. a timing means responsive to said first output signal and to a full scale count in said counter and operative to reset said ramp generator upon the occurrence of said full scale count, and reset and start said counter upon the occurrence of said first output signal, wherein said timing means comprises; i. a second detector responsive to such full scale count and operative to generate a second output signal for resetting said ramp generator upon the occurrence of said full scale count; and ii. means responsive to said second and first output signals and operative to reset said counter and said second detector upon the occurrence of said second output signal and start said counter upon the occurrence of said first output signal; f. a compare means responsive to said analog input signal and operative to generate a compare signal when said analog input signal is equal to said ramp signal; and g. a buffer means responsive to said compare signal and operative to transfer the count of said counter to said buffer so as to effectively produce in said buffer the digital value associated with the value of said analog input signal, wherein each channel in the multiple channel analog-to-digital converter further comprises a blocking means responsive to the output of said timing means for preventing a compare signal from transferring the count in said counter to said buffer during the period of time between the occurrence of said second output signal and said first output signal.

Claim 7

An analog-to-digital converter as set forth in claim 4 wherein said reference voltage associated with said first detecting means is equal to the zero setting of said ramp signal.