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Patent US5220275A successfully refreshed from Google Patents.
US5220275A
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Accumulator phase digitizer
Assignee: Ericsson Inc
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Filing: 1991-07-26
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Granted: 1993-06-15
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Expires: 2011-07-26
Abstract
Abstract In a phase digitizer for converting phase information of an analog signal into a digital representation, a phase accumulator stores incremental phase angle values of a reference signal. A trigger circuit which is responsive to an input signal and a sample signal generates a strobe signal which causes the incremental phase angle value stored in the phase accumulator to be transferred to a holding latch. The value of the holding latch is then transferred to an output latch which provides a digital representation of the phase angle of the input signal.
Inventors
- 👤 Bo P. Holmqvist
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 08:05
CPC Classifications
G; G01; G01R; G01R25/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
106 words
A circuit for determining at predetermined intervals, a digital value representative of the instantaneous phase of an input signal relative to a reference signal, said circuit comprising: a digital accumulating means, responsive to the reference signal that is incremented or decremented by a predetermined value upon each of the reference signal cycles to produce an accumulating value; triggering means responsive to a sampling signal and said input signal for generating a firing pulse; holding register means for recording said accumulating value upon occurrence of said firing pulse; and output means responsive to said sampling signal for outputting said holding register contents at said predetermined sampling intervals.
Claim 2
Dependent Claim
106 words
A circuit for determining at predetermined intervals, a digital value representative of the instantaneous phase of an input signal relative to a reference signal, said circuit comprising: a digital accumulating means, responsive to the reference signal that is incremented or decremented by a predetermined value upon each of the reference signal cycles to produce an accumulating value; triggering means responsive to a sampling signal and said input signal for generating a firing pulse; holding register means for recording said accumulating value upon occurrence of said firing pulse; and output means responsive to said sampling signal for outputting said holding register contents at said predetermined sampling intervals.
Claim 3
Dependent Claim
61 words
A circuit according to claim 1 wherein said trigger circuit includes an arm input for receiving the sampling signal and a trigger input for receiving the input signal, such that a fire pulse is generated in response to the transition in the input signal, thereby causing the transfer of the accumulating value of the digital accumulating means to the holding means.
Claim 4
Dependent Claim
26 words
An electrical circuit according to claim 2 which further includes differentiating means for converting a sequence of digital phase values to a sequence of frequency estimates.
Claim 5
Dependent Claim
58 words
A circuit according to claim 1 wherein said digital accumulating means includes means for calculating at least two accumulating values, one accumulating value for each reference signal half cycle, and said trigger circuit selects the correct accumulating value depending upon the state of the reference signal at a transition of the input signal, wherein the resolution is doubled.
Claim 6
Dependent Claim
66 words
A circuit according to claim 1 which is responsive to more than one transition of the input signal per input signal period to generate the firing pulse which causes latching of the accumulating value into the holding means, and which further includes means for compensating the accumulating value by adding or subtracting an offset corresponding to an actual trigger event relative to a standard trigger event.
Claim 7
Dependent Claim
37 words
A circuit according to claim 1 wherein said digital accumulating means includes binary counting means, which is read on the same transition of the input signal, for adding or subtracting compensation values together with the accumulating values.
Claim 8
Dependent Claim
45 words
A circuit according to claim 1 wherein said digital accumulating means includes a main counter and a compensation counter; and said holding register means includes two reading means, a first means for reading said main counter and a second means for reading said compensation counter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-14 | 1996-12-14 | 1997-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-14 | 2000-12-14 | 2001-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-14 | 2004-12-14 | 2005-06-15 | $7700.00 | Window Closed / Lapsed |