US5218712A
Expired / Lapsed
US
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Providing a data processor with a user-mode accessible mode of operations in which the processor performs processing operations without interruption
Assignee: Hewlett Packard Development Co LP
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Filing: 1990-07-11
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Granted: 1993-06-08
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Expires: 2010-07-11
Abstract
Abstract In a data processing system employing microcode techniques, complex sequences of microinstructions can be initiated by application of a single macroinstruction. These complex sequences of microinstructions are typically noninterruptible and therefore the execution of a macroinstruction is atomic (i.e., executed as a single entity). Data processing systems that do not employ microcode typically have simpler macroinstruction sets that do not provide for a similar atomicity for complex instruction sequences. In order to obtain the same atomicity of instruction execution and to provide a nonmicrocoded data processing system with the capability to execute complex instruction sequences as an atomic operation, the nonmicrocoded data processing system is provided with a third mode, in addition to the (nonprivileged) user mode and the (privileged) kernel mode, of operation that permits the execution of instruction sequences with interrupting events disabled and certain functions and apparatus enabled to facilitate instruction sequence execution.
Inventors
- 👤 David N. Cutler
- 👤 David A. Orbits
- 👤 Dileep Bhandarkar
- 👤 Wayne Cardoza
- 👤 Richard T. Witek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:36
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8061; G06F15/8069; G06F9/30; G06F9/30145; G06F9/3017; G06F9/30174; G06F9/30181; G06F9/30189; G06F9/44; G06F9/455; G06F9/45533; G06F9/4843
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
175 words
A data processor for processing programs and for servicing interrupt requests that are applied to said data processor, comprising: processing means for performing processing operations in at least three privilege modes, including a user mode, a kernel mode, and a third mode; control means for controlling said processing means in relation to said privilege modes, said control means enabling said processing means to temporarily suspend said processing operations and service said interrupt requests when said processing means is processing operations in either the user mode or the kernel mode, and inhibiting said processing means from suspending said processing operations and servicing said interrupt requests when said processing means is processing operations in the third mode; and said control means including means responsive to a selected instruction processed by said processing means when said processing means is processing operations in said user mode for causing said processing means to switch from said user mode to said third mode and atomically execute a sequence of instructions in said third mode that is associated with said selected instruction.
Claim 2
Dependent Claim
175 words
A data processor for processing programs and for servicing interrupt requests that are applied to said data processor, comprising: processing means for performing processing operations in at least three privilege modes, including a user mode, a kernel mode, and a third mode; control means for controlling said processing means in relation to said privilege modes, said control means enabling said processing means to temporarily suspend said processing operations and service said interrupt requests when said processing means is processing operations in either the user mode or the kernel mode, and inhibiting said processing means from suspending said processing operations and servicing said interrupt requests when said processing means is processing operations in the third mode; and said control means including means responsive to a selected instruction processed by said processing means when said processing means is processing operations in said user mode for causing said processing means to switch from said user mode to said third mode and atomically execute a sequence of instructions in said third mode that is associated with said selected instruction.
Claim 3
Dependent Claim
27 words
The data processor of claim 1 wherein instruction sequences executing in said third mode of operation are stored in a reserved portion of a main memory unit.
Claim 4
Dependent Claim
34 words
The data processor of claim 1 wherein said data processor utilizes virtual addressing techniques, said virtual addressing techniques being disabled for instruction stream references during operation by said data processor in said third mode.
Claim 5
Dependent Claim
25 words
The data processor of claim 1 wherein said control means enables procedures responsive to interrupting events to be executed in said third mode of operation.
Claim 6
Dependent Claim
32 words
The data processor of claim 1 wherein said control means enable said third mode of operation to be entered from said user mode of operation and from said kernel mode of operation.
Claim 7
Dependent Claim
38 words
The data processor of claim 1 wherein said data processor has a plurality of registers, said control means enabling, said processing means to use said registers only when said data processor is in said third mode of operation.
Claim 8
Dependent Claim
34 words
The data processor of claim 1 wherein said data processor includes apparatus for responding to interrupt conditions, said control means disabling, said interrupt responsive apparatus when said data processor is in said third mode.
Claim 9
Dependent Claim
56 words
The data processor of claim 1 wherein said control means enables said processing means to execute a plurality of overlapping instructions in said user mode and said kernel mode, said control means enabling, said processing means to complete execution of all currently executing instructions in said user and kernel mode prior to entering said third mode.
Claim 10
Dependent Claim
41 words
The data processor of claim 1 wherein the control means enables the processing means to execute non-privileged instructions when operating in the user mode privileged or non-privileged instructions in the kernel mode, and non-interruptible sequences of instructions in the third mode.
Claim 11
Dependent Claim
23 words
The data processor of claim 9 wherein said noninterruptible sequences of instructions include special instructions in addition to said privileged and nonprivileged instructions.
Claim 12
Dependent Claim
26 words
The data processor of claim 9 wherein said execution of said noninterruptible sequences of instructions is a response to an exception and to an interrupt event.
Claim 13
Dependent Claim
36 words
The data processor of claim 1 wherein said control means enables said processor means to process operations in said user mode and then in said third mode, without performing an intermediate operation in said kernel mode.
Claim 14
Dependent Claim
21 words
The data processor of claim 1 wherein said operations processed in said third mode are under the control of a user.
Claim 15
Dependent Claim
24 words
The data processor of claim 1 wherein said operations processed in said third mode are the result of instructions contained in an applications program.
Claim 16
Dependent Claim
24 words
The processor of claim 1 wherein said processing means does not include microcode for performing said operations that are processed in said third mode.
Claim 17
Dependent Claim
19 words
The processor of claim 1 wherein said control means is adapted to control different types of said processing means.
Claim 18
Dependent Claim
31 words
The processor of claim 16 wherein at least one of said different types of processing means does not include microcode for performing said operations that are processed in said third mode.
Claim 19
Independent Claim
131 words
A method of operating a data processor, comprising the steps of: enabling said processor to perform processing operations in at least three privilege modes, including a user mode, a kernel mode, and a third mode; enabling said processor to temporarily suspend said processing operations and service interrupt requests when said processor is processing operations in either the user mode or the kernel mode; inhibiting said processor from suspending said processing operations and servicing interrupt requests when said processor is processing operations in the third mode; and causing said processor, when processing operations in said user mode, to respond to a selected instruction by switching from said user mode to said third mode and then atomically executing a sequence of instructions in said third mode that is associated with said selected instruction.
Claim 20
Independent Claim
131 words
A method of operating a data processor, comprising the steps of: enabling said processor to perform processing operations in at least three privilege modes, including a user mode, a kernel mode, and a third mode; enabling said processor to temporarily suspend said processing operations and service interrupt requests when said processor is processing operations in either the user mode or the kernel mode; inhibiting said processor from suspending said processing operations and servicing interrupt requests when said processor is processing operations in the third mode; and causing said processor, when processing operations in said user mode, to respond to a selected instruction by switching from said user mode to said third mode and then atomically executing a sequence of instructions in said third mode that is associated with said selected instruction.
Claim 21
Dependent Claim
18 words
The method of claim 18 wherein said method is adapted to operate different types of said data processor.
Claim 22
Dependent Claim
30 words
The method of claim 19 wherein at least one of said types of data processor does not include microcode for performing said operations that are processed in said third mode.
Claim 23
Independent Claim
103 words
A method of operating a data processor which executes instructions in a user mode of operation and a kernel mode of operation, comprising the steps of: allowing said processor to temporarily suspend executing said instructions and service interrupt requests when said processor is operating in said user mode or said kernel mode; and causing said processor to respond to a predetermined instruction executed in said user mode by executing a selected sequence of instructions, and inhibiting said processor from suspending execution of said sequence and servicing interrupt requests while said processor is executing said sequence so that said processor executes said sequence atomically.
Claim 24
Independent Claim
103 words
A method of operating a data processor which executes instructions in a user mode of operation and a kernel mode of operation, comprising the steps of: allowing said processor to temporarily suspend executing said instructions and service interrupt requests when said processor is operating in said user mode or said kernel mode; and causing said processor to respond to a predetermined instruction executed in said user mode by executing a selected sequence of instructions, and inhibiting said processor from suspending execution of said sequence and servicing interrupt requests while said processor is executing said sequence so that said processor executes said sequence atomically.
Claim 25
Dependent Claim
18 words
The method of claim 21 wherein said method is adapted to operate different types of said data processor.
Claim 26
Dependent Claim
34 words
The method of claim 22 wherein said data processor performs a selected operation by executing said sequence, at least one of said types of data processor not including microcode for performing said selected operation.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-07 | 1996-12-07 | 1997-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-07 | 2000-12-07 | 2001-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-07 | 2004-12-07 | 2005-06-08 | $7700.00 | Window Closed / Lapsed |